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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b0470f11088sm327758666b.111.2025.09.04.07.50.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Sep 2025 07:50:47 -0700 (PDT) Message-ID: <18092427-3a4a-4fb2-9f75-675de98957d4@oss.qualcomm.com> Date: Thu, 4 Sep 2025 16:50:45 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V5 4/4] arm64: dts: qcom: sm8550: Add max-sd-hs-hz property To: Krzysztof Kozlowski , Sarthak Garg , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Adrian Hunter Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com References: <20250903080404.3260135-1-quic_sartgarg@quicinc.com> <20250903080404.3260135-5-quic_sartgarg@quicinc.com> <6deac56f-e21a-4447-bfa7-a414084676b8@kernel.org> <23c29fb7-c0a4-4519-9b8d-e68255b83a10@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=OemYDgTY c=1 sm=1 tr=0 ts=68b9a74a cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=c_I0RgxThugTXrF3K4IA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: djuVkWjDFBDipUvwACQK9QFcJmDoT6M6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAyNCBTYWx0ZWRfXz/yZYJo6UJtq wCJ4yrqwYnE4EeaKzjSSfl0t4G7BNAST1wZTQAL55g8F+1e2bNvH7lm921TE5lA3qJm8Q9zuK69 OREujB2ke15B/ZmTz3C4/GJa869YM+ERIT9mfhMcni4Z/VFA4301Ru9RyVYi17ElmJF5Vq9KILM +cW6ZK/Hr83sZwo8403r8b7a6eZ4bXPGjO1k0UkqZFI7p8prENGVHmIEXw/837RD9PIfKLdG5nw fSRgAKMPOg+TVJfiQqxDMe5qez67DHqegVViMTfimMfYbVX+tBV7xAy6duqSdNl68a7L4s5NfeK XcNizjx/yAvFk4b++WL5zAY+eMfM5Mw1hlfSJKgT64tGE/c20mBfPmStvjzCe/X5KS3O3YGiFUf 7XfmZYfS X-Proofpoint-ORIG-GUID: djuVkWjDFBDipUvwACQK9QFcJmDoT6M6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-04_05,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 priorityscore=1501 adultscore=0 clxscore=1015 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300024 On 9/4/25 3:07 PM, Krzysztof Kozlowski wrote: > On 04/09/2025 14:27, Konrad Dybcio wrote: >> On 9/4/25 12:52 PM, Krzysztof Kozlowski wrote: >>> On 04/09/2025 12:51, Krzysztof Kozlowski wrote: >>>> On 04/09/2025 10:36, Konrad Dybcio wrote: >>>>> On 9/3/25 10:21 AM, 'Krzysztof Kozlowski' via kernel wrote: >>>>>> On 03/09/2025 10:04, Sarthak Garg wrote: >>>>>>> Due to board-specific hardware constraints particularly related >>>>>>> to level shifter in this case the maximum frequency for SD High-Speed >>>>>>> (HS) mode must be limited to 37.5 MHz to ensure reliable operation of SD >>>>>>> card in HS mode. >>>>>>> >>>>>>> This is achieved by introducing the `max-sd-hs-hz` property in the >>>>>>> device tree, allowing the controller to operate within safe frequency >>>>>>> limits for HS mode. >>>>>>> >>>>>> >>>>>> Probably we will now replicate the same discussion... And it will be >>>>>> happening every time you send the same and not reflect it in commit msg. >>> >>> Just to emphasize this - it will happen EVERY time. >>> >>>>>> >>>>>> Bindings say board setup, this commit msg says board config, but the >>>>>> patch says SoC. This is not correct. >>>>> >>>>> Both are correct, looking at the problem from two perspectives. >>>>> >>>>> The bindings description mentions board-specific limitations (e.g. because >>>>> "the board's electrical design does not allow one to achieve the full rated >>>>> frequency that the SoC can otherwise do, in a stable way") >>>>> >>>>> Here the author tries to argue that almost all SM8550 boards are broken >>>>> in this sense, because the reference design did not feature the required >>>>> passive components, making most (derivative) designs sort of "broken by >>>>> default" - and only some (if any?) vendors decided to go with the >>>>> additional components required to lift this limitation. >>>>> >>>>> This in turn makes it fair to assume the developer experience would benefit >>>>> from having the SD card high speed modes always work (with the slight speed >>>>> cap which may not be required for the 1 or 2 designs that took the extra >>>>> step) without each board DT creator having to track down this property >>>>> separately. >>>> >>>> And then if you send same v3, I will ask the same. Can the author >>> >>> v3 -> v6 >> >> So, would you be accepting of this patch if the commit message was: >> >> arm64: dts: qcom: sm8550: Limit max SD HS mode frequency by default >> >> Due to an implementation detail in this SoC, additional passive >> electrical components are required to achieve the maximum rated speed >> of the SD controller when paired with a High-Speed SD Card. Without them, >> the clock frequency must be limited to 37.5 MHz for link stability. >> >> Because the reference design does not contain these components, most >> (derivative) boards do not have them either. To accommodate for that, >> apply the frequency limit by default and delegate lifting it to the >> odd boards that do contain the necessary onboard hardware. > Yes, it is an excellent explanation. Sarthak, if you believe what I said is accurate, feel free to copy-paste as is Konrad