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Mon, 22 Jul 2024 06:36:57 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-568-g843fbadbe-fm-20240701.003-g843fbadb Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <1811a5de-1a7f-46a9-b8ad-a76ec51f3a23@app.fastmail.com> In-Reply-To: <87h6chk9xo.fsf@BLaptop.bootlin.com> References: <20240719-smp_i6500-v1-1-8738e67d4802@bootlin.com> <302ca8fb-0185-4872-9d82-d472854e5a43@app.fastmail.com> <6cbe8375-c11d-4fbf-8e4f-b15828ac3480@app.fastmail.com> <87jzhdkask.fsf@BLaptop.bootlin.com> <87h6chk9xo.fsf@BLaptop.bootlin.com> Date: Mon, 22 Jul 2024 18:36:37 +0800 From: "Jiaxun Yang" To: "Gregory CLEMENT" , "Thomas Bogendoerfer" , "paulburton@kernel.org" Cc: "linux-mips@vger.kernel.org" , linux-kernel@vger.kernel.org, =?UTF-8?Q?Th=C3=A9o_Lebrun?= , "Vladimir Kondratiev" , "Tawfik Bayouk" , "Thomas Petazzoni" Subject: Re: [PATCH] MIPS: SMP-CPS: Fix address for GCR_ACCESS register for I6500 Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82024=E5=B9=B47=E6=9C=8822=E6=97=A5=E4=B8=83=E6=9C=88 =E4=B8=8B=E5= =8D=886:17=EF=BC=8CGregory CLEMENT=E5=86=99=E9=81=93=EF=BC=9A > Gregory CLEMENT writes: > >> Hello Jiaxun, >> >>> =E5=9C=A82024=E5=B9=B47=E6=9C=8820=E6=97=A5=E4=B8=83=E6=9C=88 =E4=B8= =8A=E5=8D=8811:13=EF=BC=8CJiaxun Yang=E5=86=99=E9=81=93=EF=BC=9A >>>> =E5=9C=A82024=E5=B9=B47=E6=9C=8819=E6=97=A5=E4=B8=83=E6=9C=88 =E4=B8= =8B=E5=8D=8810:14=EF=BC=8CGregory CLEMENT=E5=86=99=E9=81=93=EF=BC=9A >>>>> Unlike most other MIPS CPUs, the I6500 CPUs have different address >>>>> offsets for the Global CSR Access Privilege register. In the "MIPS= 64 >>>>> I6500 Multiprocessing System Programmer's Guide," it is stated that >>>>> "the Global CSR Access Privilege register is located at offset 0x0= 120" >>>>> in section 5.4. >>>>> >>>>> However, this is not the case for other MIPS64 CPUs such as the >>>>> P6600. In the "MIPS64=C2=AE P6600 Multiprocessing System Software = User's >>>>> Guide," section 6.4.2.6 states that the GCR_ACCESS register has an >>>>> offset of 0x0020. >>>> >>>> Hi Gregory, >>>> >>>> I confirmed this is a CM3 feature rather than CPU core (Samruai) fe= ature. >>> >>> Oh I=E2=80=99m not really sure if it=E2=80=99s CM 3.5 only. >>> >>> Let me check this Monday once I can checkout old design database for >>> I6400. >> >> Ok, so I am waiting for your feedback :) >> And I am also trying to see if I can find the datasheet for I6400. >>> >>> Hardware resets GCR_ACCESS to the most permissive value so I assume >>> it=E2=80=99s your bootloader doing wired hacks. > > I found an I6400 datasheet [1] and in the "5.4 CM Register Access > Permissions" paragraph, it is written "the Global CSR Access Privilege > register located at offset 0x0120". So it has the same offset as the > I6500. Yes, I hand confirmed this modification was made to CM block at transiti= on from CM2.5 to CM3. Other unannounced CM3 products (Daiymo, King for people knowing codename= s) have this change as well. So for this modification, you can safely do: mips_cm_revision() >=3D CM_REV_CM3 And perhaps name this GCR after access_cm3. Thanks - Jiaxun > > Gregory > > [1]:=20 > https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MIPS_Warri= or_I6400_ProgrammerGuide_MD01196_P_1.00.pdf > >> >> Indeed, other bootloaders seem to not modify it, so that's why I think >> the issue was never detected until now. However, we want to be as >> independent as possible from the bootloader, so we really need to fix >> it. >> >> Thanks for your review! >> >> Gregory >> --=20 - Jiaxun