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Thu, 19 Jun 2025 09:04:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEjJXAklTpU4bxpt+jnWBfHNJB4kATINyoW2fUcIAggJV9+NymIlKk9BuBUHb5XP9WcmOt80w== X-Received: by 2002:a17:902:ecce:b0:22f:b6d6:2737 with SMTP id d9443c01a7336-2366b32e726mr380403205ad.10.1750349087399; Thu, 19 Jun 2025 09:04:47 -0700 (PDT) Received: from [192.168.40.164] ([70.105.235.240]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2365deca379sm121411835ad.210.2025.06.19.09.04.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Jun 2025 09:04:46 -0700 (PDT) Message-ID: <18151eb8-60ec-438b-b9fb-026efc8b848d@redhat.com> Date: Thu, 19 Jun 2025 12:03:29 -0400 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 4/5] KVM: arm64: Allow cacheable stage 2 mapping using VMA flags Content-Language: en-US To: Ankit Agrawal , Jason Gunthorpe , Catalin Marinas Cc: "maz@kernel.org" , "oliver.upton@linux.dev" , "joey.gouly@arm.com" , "suzuki.poulose@arm.com" , "yuzenghui@huawei.com" , "will@kernel.org" , "ryan.roberts@arm.com" , "shahuang@redhat.com" , "lpieralisi@kernel.org" , "david@redhat.com" , "seanjc@google.com" , Aniket Agashe , Neo Jia , Kirti Wankhede , Krishnakant Jaju , "Tarun Gupta (SW-GPU)" , Vikram Sethi , Andy Currid , Alistair Popple , John Hubbard , Dan Williams , Zhi Wang , Matt Ochs , Uday Dhoke , Dheeraj Nigam , "alex.williamson@redhat.com" , "sebastianene@google.com" , "coltonlewis@google.com" , "kevin.tian@intel.com" , "yi.l.liu@intel.com" , "ardb@kernel.org" , "akpm@linux-foundation.org" , "gshan@redhat.com" , "linux-mm@kvack.org" , "tabba@google.com" , "qperret@google.com" , "kvmarm@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "maobibo@loongson.cn" References: <20250618065541.50049-1-ankita@nvidia.com> <20250618065541.50049-5-ankita@nvidia.com> <20250618163836.GA1629589@nvidia.com> From: Donald Dutile In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/19/25 8:14 AM, Ankit Agrawal wrote: > Considering the feedback, I think we may do the following here: > 1. Rename the device variable to S2_noncacheable to represent if the S2 is going to be marked non cacheable. Otherwise S2 will be mapped NORMAL. > 2. Detect what PFN has to be marked S2_noncacheable. If a PFN is not in the kernel map, mark as S2 except for PFNMAP + VMA cacheable. Q: 'mark as S2 except'... should be 'mark as S2_noncacheable' ? > 3. Prohibit cacheable PFNMAP if hardware doesn't support FWB and CACHE DIC. > 4. Prohibit S2 non cached mapping for cacheable VMA for all cases, whether pre-FWB hardware or not.