From: Thiago Macieira <thiago.macieira@intel.com>
To: "Chang S. Bae" <chang.seok.bae@intel.com>
Cc: <bp@suse.de>, <luto@kernel.org>, <tglx@linutronix.de>,
<mingo@kernel.org>, <x86@kernel.org>, <len.brown@intel.com>,
<dave.hansen@intel.com>, <jing2.liu@intel.com>,
<ravi.v.shankar@intel.com>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v7 12/26] x86/fpu/xstate: Use feature disable (XFD) to protect dynamic user state
Date: Tue, 13 Jul 2021 12:13:16 -0700 [thread overview]
Message-ID: <1817232.MPthNTNLIG@tjmaciei-mobl5> (raw)
In-Reply-To: <20210710130313.5072-13-chang.seok.bae@intel.com>
On Saturday, 10 July 2021 06:02:59 PDT Chang S. Bae wrote:
> diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
> index a58800973aed..f45b2cefd6cf 100644
> --- a/arch/x86/kernel/traps.c
> +++ b/arch/x86/kernel/traps.c
> @@ -1112,6 +1112,44 @@ DEFINE_IDTENTRY(exc_device_not_available)
[cut]
> + /* Raise a signal when it failed to handle.
> */ + if (err)
> + force_sig(SIGSEGV);
> + }
> + return;
Hello Chang
Can I make a suggestion that you send a different signal than SIGSEGV for the
failure of unauthorised instructions? I would recommend SIGILL. Additionally,
please consider a new ILL_* constant for the si_code field.
I have multiple reasons for that:
1) the XFD failure is not a memory issue, so SIGSEGV is not really
appropriate, despite coming from an #NM interrupt
2) SIGILL is sent for the AMX instructions in other circumstances, due to CPU
#UD, notably:
- running on a CPU without AMX support
- running under an OS that did not enable the AMX state in XCR0 (like Linux
before this patch series)
When a developer is debugging code and sees a SIGILL on a valid instruction
stream in disassembly, they know they've got to code they should never have
got to, bypassing CPU checks. Forgetting to ask for permission is now a
variant of that case.
3) the very first AMX instruction to cause the #NM is likely going to be an
LDTILECFG or TILELOADD, which are memory-related instructions, so may #GP for
using bad pointers (and LDTILECFG can #GP for bad tile configurations).
Knowing that the issue was the instruction itself instead of the pointer or
data being loaded is going to come in handy.
4) SIGSEGV will also be sent for another reason by the kernel. Your cover
message had:
> 4. Applications touching AMX without permission results in process exit.
>
> Armed XFD results in #NM, results in SIGSEGV, typically resulting in
> process exit.
> 6. NM handler allocation failure results in process exit.
>
> If the #NM handler can not allocate the 8KB buffer, the task will
> receive a SIGSEGV at the instruction that took the #NM fault, typically
> resulting in process exit.
Knowing that it was caused by reaching code that shouldn't have been reached,
instead of an OOM issue, is handy.
Do note that this SIGSEGV for allocation is unlikely to happen. If the kernel
is under memory pressure, the OOM killer will probably kick in and may kill
(SIGKILL) this process instead. But at least #6 is a legitimate memory issue.
On the same topic, is there a way to save this state in a core dump? The FS
and GS bases would also be very handy.
--
Thiago Macieira - thiago.macieira (AT) intel.com
Software Architect - Intel DPG Cloud Engineering
next prev parent reply other threads:[~2021-07-13 19:13 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-10 13:02 [PATCH v7 00/26] x86: Support Intel Advanced Matrix Extensions Chang S. Bae
2021-07-10 13:02 ` [PATCH v7 01/26] x86/fpu/xstate: Modify the initialization helper to handle both static and dynamic buffers Chang S. Bae
2021-07-10 13:02 ` [PATCH v7 02/26] x86/fpu/xstate: Modify state copy helpers " Chang S. Bae
2021-07-10 13:02 ` [PATCH v7 03/26] x86/fpu/xstate: Modify address finders " Chang S. Bae
2021-07-10 13:02 ` [PATCH v7 04/26] x86/fpu/xstate: Add a new variable to indicate dynamic user states Chang S. Bae
2021-07-10 13:02 ` [PATCH v7 05/26] x86/fpu/xstate: Add new variables to indicate dynamic XSTATE buffer size Chang S. Bae
2021-07-10 13:02 ` [PATCH v7 06/26] x86/fpu/xstate: Calculate and remember dynamic XSTATE buffer sizes Chang S. Bae
2021-07-10 13:02 ` [PATCH v7 07/26] x86/fpu/xstate: Convert the struct fpu 'state' field to a pointer Chang S. Bae
2021-07-10 13:02 ` [PATCH v7 08/26] x86/fpu/xstate: Introduce helpers to manage the XSTATE buffer dynamically Chang S. Bae
2021-07-10 13:02 ` [PATCH v7 09/26] x86/fpu/xstate: Update the XSTATE save function to support dynamic states Chang S. Bae
2021-07-10 13:02 ` [PATCH v7 10/26] x86/fpu/xstate: Update the XSTATE buffer address finder " Chang S. Bae
2021-07-10 13:02 ` [PATCH v7 11/26] x86/fpu/xstate: Update the XSTATE context copy function " Chang S. Bae
2021-07-10 13:02 ` [PATCH v7 12/26] x86/fpu/xstate: Use feature disable (XFD) to protect dynamic user state Chang S. Bae
2021-07-13 19:13 ` Thiago Macieira [this message]
2021-07-17 15:47 ` Bae, Chang Seok
2021-07-10 13:03 ` [PATCH v7 13/26] x86/fpu/xstate: Support ptracer-induced XSTATE buffer expansion Chang S. Bae
2021-07-10 13:03 ` [PATCH v7 14/26] x86/arch_prctl: Create ARCH_SET_XSTATE_ENABLE/ARCH_GET_XSTATE_ENABLE Chang S. Bae
2021-07-10 13:03 ` [PATCH v7 15/26] x86/fpu/xstate: Support both legacy and expanded signal XSTATE size Chang S. Bae
2021-07-10 13:03 ` [PATCH v7 16/26] x86/fpu/xstate: Adjust the XSAVE feature table to address gaps in state component numbers Chang S. Bae
2021-07-10 13:03 ` [PATCH v7 17/26] x86/fpu/xstate: Disable XSTATE support if an inconsistent state is detected Chang S. Bae
2021-07-10 13:03 ` [PATCH v7 18/26] x86/cpufeatures/amx: Enumerate Advanced Matrix Extension (AMX) feature bits Chang S. Bae
2021-07-10 13:03 ` [PATCH v7 19/26] x86/fpu/amx: Define AMX state components and have it used for boot-time checks Chang S. Bae
2021-07-10 13:03 ` [PATCH v7 20/26] x86/fpu/amx: Initialize child's AMX state Chang S. Bae
2021-07-10 13:03 ` [PATCH v7 21/26] x86/fpu/amx: Enable the AMX feature in 64-bit mode Chang S. Bae
2021-07-10 13:03 ` [PATCH v7 22/26] x86/fpu/xstate: Skip writing zeros to signal frame for dynamic user states if in INIT-state Chang S. Bae
2021-07-10 13:03 ` [PATCH v7 23/26] selftest/x86/amx: Test cases for the AMX state management Chang S. Bae
2021-07-10 13:03 ` [PATCH v7 24/26] x86/insn/amx: Add TILERELEASE instruction to the opcode map Chang S. Bae
2021-07-10 13:03 ` [PATCH v7 25/26] intel_idle/amx: Add SPR support with XTILEDATA capability Chang S. Bae
2021-07-16 17:34 ` Rafael J. Wysocki
2021-07-16 17:37 ` Bae, Chang Seok
2021-07-10 13:03 ` [PATCH v7 26/26] x86/fpu/xstate: Add a sanity check for XFD state when saving XSTATE Chang S. Bae
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