From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752118AbbHTIYl (ORCPT ); Thu, 20 Aug 2015 04:24:41 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:50404 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750981AbbHTIYh (ORCPT ); Thu, 20 Aug 2015 04:24:37 -0400 X-AuditID: cbfee68f-f793b6d000005f66-ab-55d58ec36289 Date: Thu, 20 Aug 2015 08:24:35 +0000 (GMT) From: Sarbojit Ganguly Subject: Re: Re: Re: [PATCH] arm: Adding support for atomic half word exchange To: Russell King - ARM Linux , Sarbojit Ganguly , "catalin.marinas@arm.com" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "SHARAN ALLUR sharan.allur@samsung.com" <"SHARANALLUR, "VIKRAM MUPPARTHI vikram.m@samsung.com" <"VIKRAMMUPPARTHI, "peterz@infradead.org" , "Waiman.Long@hp.com" , "WillDeacon X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrEIsWRmVeSWpSXmKPExsWyRsSkTvdw39VQg23vNS0u75rD5sDo8XmT XABjFJdNSmpOZllqkb5dAlfGi1+HWQpWOVXM/buFvYHxjEMXIweHkICKRN+kiC5GTg4JAROJ WUu/sEDYYhIX7q1n62LkAipZyihx5n8fO0zRq7drWEFsIYE5jBK3LqqDzGERUJWYOCsPJMwm oC9xev9LJhBbWMBP4vXzNcwgc0QE3rFIPF/RzA7RKy/R/mI7WBGvgKDEyZlPoBYrSfw8dw8q riyx5vN+qL3iEn8bHkHZvBIz2p9C1ctJTPsKsgDElpY4P2sDI8wDi78/horzSxy7vYMJwhaQ mHrmIFSNusTFvsNQcT6JNQvfssDU7zq1nBlmV8PG31B7JSS2tjwB+51ZQFFiSvdDdpDfmQU0 Jdbv0kf3Cq+Ap8SVX8vBYSgh0MohcWHJXLC9LEA3fJt8iGUCo+IsJD2zkIydhTAWWckCRpZV jKKpBckFxUnpRcZ6xYm5xaV56XrJ+bmbGIFJ4fS/Z/07GO8esD7EKMDBqMTDe0H4aqgQa2JZ cWXuIUZToM0TmaVEk/OBqSevJN7Q2MzIwtTE1NjI3NJMSZx3odTPYCGB9MSS1OzU1ILUovii 0pzU4kOMTBycUg2Muz+4LdC/Z6j5fl12Eu/hB1l39pxacp599eIriX+bz+peOXZEzvG9w3Er +Wf8sXlHHnC/r/+RkmSbtdL42cF40wCVAg6FWo7YxsPKsVfYOxa1a+ZkXnxcu2aO9OyXLX1f 7L2lp/D47igySlkgL7508VMH/elrHz3QMlt9rZVlzyMZo9L3p+w5lViKMxINtZiLihMB/Ym3 qQUDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrOKsWRmVeSWpSXmKPExsVy+t/tft3DfVdDDdask7e4vGsOmwOjx+dN cgGMUWk2GamJKalFCql5yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUBD lRTKEnNKgUIBicXFSvp2NkX5pSWpChn5xSW2StGG5kZ6RgZ6pkZ6hqaxVoYGBkamQDUJaRkv fh1mKVjlVDH37xb2BsYzDl2MHBxCAioSfZMiuhg5OSQETCRevV3DCmGLSVy4t54NxBYSmMMo ceuiOkg5i4CqxMRZeSBhNgF9idP7XzKB2MICfhKvn69h7mLk4hAReMci8XxFMztEr7xE+4vt YEW8AoISJ2c+YYGYryTx89w9qLiyxJrP+9kh4uISfxseQdm8EjPan0LVy0lM+wqyAMSWljg/ awMjzJ2Lvz+GivNLHLu9gwnCFpCYeuYgVI26xMW+w1BxPok1C9+ywNTvOrWcGWZXw8bfUHsl JLa2PAGHA7OAosSU7ofsIL8zC2hKrN+lj+4VXgFPiSu/lrNNYJSZhSQ1C0n3LIRuZCULGFlW MYqmFiQXFCelVxjpFSfmFpfmpesl5+duYgQnmmeLdjD+O299iFGAg1GJh/eC8NVQIdbEsuLK 3EOMEhzMSiK8fjpAId6UxMqq1KL8+KLSnNTiQ4ymwHiayCwlmpwPTIJ5JfGGxibmpsamFgaG 5uZmSuK8/8/lhggJpCeWpGanphakFsH0MXFwSjUwVkw7m1I727TFRUBXiU1RyU7N67PKC/3I zt2xwT41eofWsj5otjuY3tVxMnbPsUKri6sWuyTv4ngpudr75LmGIymdRvtcrBcnzXrH22Di VFYlsPGWyJEPKvr9oa+Yby9nzV487RkP1+uLPy1MNrMv3RVidmpr+t11qVuyX28RuXhA/+sE zpAoJZbijERDLeai4kQAGGs7nEoDAAA= DLP-Filter: Pass X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id t7K8OlWl026393 Hello Russell, My apologies for the accidental HTML formatting. I have reconfigured my e-mail client to use text-only format by default. Here is the patch and its description. Since 16 bit half word exchange was not there and MCS based qspinlock by Waiman's xchg_tail() requires an atomic exchange on a half word, here is a small modification to __xchg() code to support the exchange. ARMv6 and lower does not have support for LDREXH, so we need to make sure things do not break when we're compiling on ARMv6. Signed-off-by: Sarbojit Ganguly --- arch/arm/include/asm/cmpxchg.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 1692a05..547101d 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -50,6 +50,24 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size : "r" (x), "r" (ptr) : "memory", "cc"); break; +#if !defined (CONFIG_CPU_V6) + /* + * Halfword exclusive exchange + * This is new implementation as qspinlock + * wants 16 bit atomic CAS. + * This is not supported on ARMv6. + */ + case 2: + asm volatile("@ __xchg2 " + "1: ldrexh %0, [%3] " + " strexh %1, %2, [%3] " + " teq %1, #0 " + " bne 1b" + : "=&r" (ret), "=&r" (tmp) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; +#endif case 4: asm volatile("@ __xchg4 " "1: ldrex %0, [%3] " Regards, Sarbojit ------- Original Message ------- Sender : Russell King - ARM Linux Date : Aug 20, 2015 13:49 (GMT+05:30) Title : Re: Re: [PATCH] arm: Adding support for atomic half word exchange This email is unreadable. Do NOT use html email when discussing linux matters. Many mailing lists will reject or discard your message. On Thu, Aug 20, 2015 at 06:47:50AM +0000, Sarbojit Ganguly wrote: > > > > > > > > > My apologies, the e-mail editor was not configured properly. CC'ed to relevant maintainers and reposting once again with proper formatting. Since 16 bit half word exchange was not there and MCS based qspinlock by Waiman's xchg_tail() requires an atomic exchange on a half word, here is a small modification to __xchg() code to support the exchange. ARMv6 and lower does not have support for LDREXH, so we need to make sure things do not break when we're compiling on ARMv6. Signed-off-by: Sarbojit Ganguly --- arch/arm/include/asm/cmpxchg.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 1692a05..547101d 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -50,6 +50,24 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size : "r" (x), "r" (ptr) : "memory", "cc"); break; +#if !defined (CONFIG_CPU_V6) + /* + * Halfword exclusive exchange + * This is new implementation as qspinlock + * wants 16 bit atomic CAS. + * This is not supported on ARMv6. + */ + case 2: + asm volatile("@ __xchg2 " + "1: ldrexh %0, [%3] " + " strexh %1, %2, [%3] " + " teq %1, #0 " + " bne 1b" + : "=&r" (ret), "=&r" (tmp) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; +#endif case 4: asm volatile("@ __xchg4 " "1: ldrex %0, [%3] " Regards, Sarbojit ------- Original Message ------- Sender : Catalin Marinas Date : Aug 19, 2015 21:43 (GMT+05:30) Title : Re: [PATCH] arm: Adding support for atomic half word exchange On Tue, Aug 18, 2015 at 09:17:53AM +0100, Sarbojit Ganguly wrote: > > > Since 16 bit half word exchange was not there and MCS based qspinlock by Waiman's xchg_tail() requires an atomic exchange on a half word, here is a small modification to __xchg() code to support the exchange. > ARMv6 and lower does not have support for LDREXH, so we need to make sure things do not break when we're compiling on ARMv6. First of all, please wrap the text appropriately. Secondly, you need to cc the relevant maintainer and mailing list (try running ./scripts/get_maintainer.pl on this patch to get some hints). -- Catalin > > > 감사합니다 > 사보짓 선임 삼성 전자 > ----------------------------------------------------------------------+ > The Tao lies beyond Yin and Yang. It is silent and still as a pool of water. | > It does not seek fame, therefore nobody knows its presence. | > It does not seek fortune, for it is complete within itself. | > It exists beyond space and time. | > ----------------------------------------------------------------------+ > > > > > > -- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net. 감사합니다 사보짓 선임 삼성 전자 ----------------------------------------------------------------------+ The Tao lies beyond Yin and Yang. It is silent and still as a pool of water. | It does not seek fame, therefore nobody knows its presence. | It does not seek fortune, for it is complete within itself. | It exists beyond space and time. | ----------------------------------------------------------------------+{.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I