From: Valdis.Kletnieks@vt.edu
To: Liang Li <liang.z.li@intel.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
tglx@linutronix.de, mingo@redhat.com,
kirill.shutemov@linux.intel.com, dave.hansen@linux.intel.com,
guangrong.xiao@linux.intel.com, pbonzini@redhat.com,
rkrcmar@redhat.com
Subject: Re: [PATCH RFC 0/4] 5-level EPT
Date: Thu, 29 Dec 2016 15:38:36 -0500 [thread overview]
Message-ID: <181888.1483043916@turing-police.cc.vt.edu> (raw)
In-Reply-To: <1483003563-25847-1-git-send-email-liang.z.li@intel.com>
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On Thu, 29 Dec 2016 17:25:59 +0800, Liang Li said:
> x86-64 is currently limited physical address width to 46 bits, which
> can support 64 TiB of memory. Some vendors require to support more for
> some use case. Intel plans to extend the physical address width to
> 52 bits in some of the future products.
Can you explain why this patchset mentions 52 bits in some places,
and 57 in others? Is it because there are currently in-process
chipsets that will do 52, but you want to future-proof it by extending
it to 57 so future chipsets won't need more work? Or is there some other
reason?
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next prev parent reply other threads:[~2016-12-29 20:39 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-29 9:25 Liang Li
2016-12-29 9:26 ` [PATCH RFC 1/4] x86: Add the new CPUID and CR4 bits for 5 level page table Liang Li
2016-12-29 9:26 ` [PATCH RFC 2/4] KVM: MMU: Rename PT64_ROOT_LEVEL to PT64_ROOT_4LEVEL Liang Li
2017-03-09 14:39 ` Paolo Bonzini
2016-12-29 9:26 ` [PATCH RFC 3/4] KVM: MMU: Add 5 level EPT & Shadow page table support Liang Li
2017-03-09 15:12 ` Paolo Bonzini
2016-12-29 9:26 ` [PATCH RFC 4/4] VMX: Expose the LA57 feature to VM Liang Li
2017-03-09 15:16 ` Paolo Bonzini
2016-12-29 20:38 ` Valdis.Kletnieks [this message]
2016-12-30 1:26 ` [PATCH RFC 0/4] 5-level EPT Li, Liang Z
2017-01-02 10:18 ` Paolo Bonzini
2017-01-17 2:18 ` Li, Liang Z
2017-03-09 14:16 ` Paolo Bonzini
2017-03-10 8:00 ` Yu Zhang
2017-01-05 13:26 ` Kirill A. Shutemov
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