From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62B54C4332F for ; Tue, 14 Nov 2023 10:58:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232833AbjKNK6E (ORCPT ); Tue, 14 Nov 2023 05:58:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232921AbjKNK5u (ORCPT ); Tue, 14 Nov 2023 05:57:50 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C12E61985 for ; Tue, 14 Nov 2023 02:57:11 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C9D0CC15; Tue, 14 Nov 2023 02:57:56 -0800 (PST) Received: from [10.1.27.144] (XHFQ2J9959.cambridge.arm.com [10.1.27.144]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1DA963F641; Tue, 14 Nov 2023 02:57:09 -0800 (PST) Message-ID: <181a25c2-219e-4af9-9f8e-e5f514bbc4b6@arm.com> Date: Tue, 14 Nov 2023 10:57:07 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 0/9] variable-order, large folios for anonymous memory Content-Language: en-GB To: Matthew Wilcox Cc: John Hubbard , Andrew Morton , Yin Fengwei , David Hildenbrand , Yu Zhao , Catalin Marinas , Anshuman Khandual , Yang Shi , "Huang, Ying" , Zi Yan , Luis Chamberlain , Itaru Kitayama , "Kirill A. Shutemov" , David Rientjes , Vlastimil Babka , Hugh Dickins , linux-mm@kvack.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20230929114421.3761121-1-ryan.roberts@arm.com> From: Ryan Roberts In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/11/2023 15:04, Matthew Wilcox wrote: > On Mon, Nov 13, 2023 at 10:19:48AM +0000, Ryan Roberts wrote: >> On 13/11/2023 05:18, Matthew Wilcox wrote: >>> My hope is to abolish the 64kB page size configuration. ie instead of >>> using the mixture of page sizes that you currently are -- 64k and >>> 1M (right? Order-0, and order-4) >> >> Not quite; the contpte-size for a 64K page size is 2M/order-5. (and yes, it is >> 64K/order-4 for a 4K page size, and 2M/order-7 for a 16K page size. I agree that >> intuitively you would expect the order to remain constant, but it doesn't). >> >> The "recommend" setting above will actually enable order-3 as well even though >> there is no HW benefit to this. So the full set of available memory sizes here is: >> >> 64K/order-0, 512K/order-3, 2M/order-5, 512M/order-13 >> >>> , that 4k, 64k and 2MB (order-0, >>> order-4 and order-9) will provide better performance. >>> >>> Have you run any experiements with a 4kB page size? >> >> Agree that would be interesting with 64K small-sized THP enabled. And I'd love >> to get to a world were we universally deal in variable sized chunks of memory, >> aligned on 4K boundaries. >> >> In my experience though, there are still some performance benefits to 64K base >> page vs 4K+contpte; the page tables are more cache efficient for the former case >> - 64K of memory is described by 8 bytes in the former vs 8x16=128 bytes in the >> latter. In practice the HW will still only read 8 bytes in the latter but that's >> taking up a full cache line vs the former where a single cache line stores 8x >> 64K entries. > > This is going to depend on your workload though -- if you're using more > 2MB than 64kB, you get to elide a layer of page table with 4k base, > rather than taking up 4 cache lines with a 64k base. True, but again depending on workload/config, you may have few levels of lookup for the 64K native case in the first place because you consume more VA bits at each level.