From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751749AbbHRISG (ORCPT ); Tue, 18 Aug 2015 04:18:06 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:56411 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750847AbbHRISD (ORCPT ); Tue, 18 Aug 2015 04:18:03 -0400 X-AuditID: cbfee68d-f79106d00000728c-76-55d2ea359a71 Date: Tue, 18 Aug 2015 08:17:52 +0000 (GMT) From: Sarbojit Ganguly Subject: [PATCH] arm: Adding support for atomic half word exchange To: "SHARANALLUR, tglx@linutronix.de, mingo@redhat.com, peterz@infradead.org, Waiman.Long@hp.com, oleg@redhat.com, linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, catalin.marinas@arm.com, "RaghavendraKT X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKIsWRmVeSWpSXmKPExsWyRsSkRtf01aVQg6XreCwu75rD5sDo8XmT XABjFJdNSmpOZllqkb5dAlfGvIYjrAW/+CrufJrK2sB4hK+LkYNDSEBFom9SRBcjJ4eEgInE nMtXmCBsMYkL99azdTFyAZUsZZToWnSUDaQepOjb9kKI+BxGieM939hBGlgEVCX6OmeD2WwC +hKn978EGyQs4CTxoLUPbJCIQCOLxIQ9E8CKhATkJdpfbAcr4hUQlDg58wkLxGYlibPN91kg 4soSp+e+YIWIy0ksmXoZ6jpeiRntT1lg4tO+rmGGsKUlzs/awAjzweLvj6Hi/BLHbu+A6hWQ mHrmIFSNusSWpReh5vNJrFn4lgWmftep5cwwuxo2/maHsCUktrY8AatnFlCUmNL9kB3CNpA4 smgOK7pfeAU8JR4u6GMGeV5CoJVDovP3L0ZIaAlIfJt8iGUCo+IsJD2zkMydhWQuspoFjCyr GEVTC5ILipPSiwz1ihNzi0vz0vWS83M3MQJTw+l/z3p3MN4+YH2IUYCDUYmH90LBpVAh1sSy 4srcQ4ymQKsnMkuJJucDE1BeSbyhsZmRhamJqbGRuaWZkjivotTPYCGB9MSS1OzU1ILUovii 0pzU4kOMTBycUg2Mogfccy//K7g554y3+MGQ6uvr43b8fXN5qvn0j/eabn0JXqfgrq5abvxr 8bck67Vqa9dvvKJ5L7zbwnWqrdhiDdkv+cf9mL+dWBoS4TXRWaDqoSf7lrlf71pJXRCZGXG4 0+DClqVT3/LJd3u7hH4uE4haZczGHHSRVe73d3+BC8Gu9fMdnBgXKLEUZyQaajEXFScCANq/ QywIAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFKsWRmVeSWpSXmKPExsVy+t/tPl2DV5dCDfZvlLe4vGsOmwOjx+dN cgGMUWk2GamJKalFCql5yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUBD lRTKEnNKgUIBicXFSvp2NkX5pSWpChn5xSW2StGG5kZ6RgZ6pkZ6hqaxVoYGBkamQDUJaRnz Go6wFvziq7jzaSprA+MRvi5GDg4hARWJvkkRIKaEgInEt+2FXYycQKaYxIV769m6GLmAKuYw Shzv+cYOkmARUJXo65wNZrMJ6Euc3v+SCcQWFnCSeNDaB9YgItDIIjFhzwSwIiEBeYn2F9vB ingFBCVOznzCArFBSeJs830WiLiyxOm5L1gh4nISS6ZeZoKweSVmtD9lgYlP+7qGGcKWljg/ awMjzKWLvz+GivNLHLu9A6pXQGLqmYNQNeoSW5ZehJrPJ7Fm4VsWmPpdp5Yzw+xq2PibHcKW kNja8gSsnllAUWJK90N2CNtA4siiOazofuEV8JR4uKCPeQKjzCwkqVlI2mchaUdWs4CRZRWj aGpBckFxUnqFkV5xYm5xaV66XnJ+7iZGcLp5tmgH47/z1ocYBTgYlXh4LxRcChViTSwrrsw9 xCjBwawkwqufChTiTUmsrEotyo8vKs1JLT7EaAqMqonMUqLJ+cBUmFcSb2hsYm5qbGphYGhu bqYkzvv/XG6IkEB6YklqdmpqQWoRTB8TB6dUA+OFoy8YWTfeO/Kkyvh7zJt9S29+W+o+pUiK u4r3z1sJ6aSthtdWrDw148mPZ2lpEywuXG5LCjni6OG4P+a+OG/54p7URqFNlvxmN39G/btu oHdnhfaV5MLQn7Y/Nz9tPNZU9++c1kydVI56Ebt1R3fF8HR1/6w6fVbmraRWjkv6JF2P3dqB ca5KLMUZiYZazEXFiQCgi7crTQMAAA== DLP-Filter: Pass X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id t7I8IDPq014757 Since 16 bit half word exchange was not there and MCS based qspinlock by Waiman's xchg_tail() requires an atomic exchange on a half word, here is a small modification to __xchg() code to support the exchange. ARMv6 and lower does not have support for LDREXH, so we need to make sure things do not break when we're compiling on ARMv6. Signed-off-by: Sarbojit Ganguly --- arch/arm/include/asm/cmpxchg.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 1692a05..547101d 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -50,6 +50,24 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size : "r" (x), "r" (ptr) : "memory", "cc"); break; +#if !defined (CONFIG_CPU_V6) + /* + * Halfword exclusive exchange + * This is new implementation as qspinlock + * wants 16 bit atomic CAS. + * This is not supported on ARMv6. + */ + case 2: + asm volatile("@ __xchg2\n" + "1: ldrexh %0, [%3]\n" + " strexh %1, %2, [%3]\n" + " teq %1, #0\n" + " bne 1b" + : "=&r" (ret), "=&r" (tmp) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; +#endif case 4: asm volatile("@ __xchg4\n" "1: ldrex %0, [%3]\n" -- Sarbojit{.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I