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Received: from VI0PR04MB12030.eurprd04.prod.outlook.com (2603:10a6:800:316::24) by MIWPR04MB533597.eurprd04.prod.outlook.com (2603:10a6:290:d7::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.546.22; Mon, 26 Oct 2026 06:27:24 +0000 Received: from VI0PR04MB12030.eurprd04.prod.outlook.com ([fe80::e428:3105:17ec:8224]) by VI0PR04MB12030.eurprd04.prod.outlook.com ([fe80::e428:3105:17ec:8224%4]) with mapi id 15.21.0546.021; Mon, 26 Oct 2026 06:27:23 +0000 Message-ID: <184780c8-6d87-4983-8399-6e509a250cfc@topic.nl> Date: Mon, 26 Oct 2026 07:27:22 +0100 User-Agent: Mozilla Thunderbird From: Mike Looijmans Subject: Re: [PATCH v2 2/6] iio: adc: ti-ads1298: fix power-up and clock handling To: Stephan Costa Barros , Jonathan Cameron CC: David Lechner , =?UTF-8?Q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Shevchenko , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Krzysztof Kozlowski , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261024231335.280955-1-stephanbrrs8@gmail.com> <20261024231335.280955-3-stephanbrrs8@gmail.com> Content-Language: en-US, nl Organization: Topic In-Reply-To: <20261024231335.280955-3-stephanbrrs8@gmail.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: K+H0wgi922mUwJ7pEfbh42CNkHz2AShuZ7dlKCc/3HixZuherCUWkB0RNvN+CvMpLH3WwBBVqze0zTHGO0aC7AizL7NlanXYYqiVroHiGSdXuN+2uhKnE72ntfwuBalKPbIcWFUZZzPWiq8Q2sJv5O+rIXYXomtM5AX/uMZryxrO7DvVl0Hwbe1gbNALHjTBX7VhO4trgC9SW5kzOGSfZpc8tJh+pYCtF+caGAh4b54UbPM3wD4iuv3uxcKTxWmlBLXcwaZ69ggGkW5uE80QqVgUOKYrRu80l5rC+1XOrEo2m7+/uvFzcRzx6SqsoCMm9CNU/Z5j2Kk0jyozigr1KZNfwEwPm/PDyJc7d1QV6GNKZjzNdeuHCOt7bQzdhvAdsJUdW28ZHJtrDwyrpvQ+gcZJV3nLjtJI8uHJeWk2AWGQKIEn82NnDjVIexRfqEfH X-OriginatorOrg: topic.nl X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Oct 2026 06:27:28.8143 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 630d31c9-6097-4406-f6fa-08df332a35b3 X-MS-Exchange-CrossTenant-Id: 449607a5-3517-482d-8d16-41dd868cbda3 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=449607a5-3517-482d-8d16-41dd868cbda3;Ip=[20.93.157.195];Helo=[westeu11-emailsignatures-cloud.codetwo.com] X-MS-Exchange-CrossTenant-AuthSource: MA3PEPF00000409.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR04MB12272 On 25-10-2026 01:13, Stephan Costa Barros wrote: > Fix three issues with the power-up sequence and the device clock: > > - The datasheet powers up the supplies first, then the clock, then > waits t_POR =3D 2^18 clock cycles (128 ms at 2.048 MHz) before the > reset. The driver enabled an external clock and the vref supply > before AVDD, reset right away, and did not wait for the 150 ms > start-up of the internal reference. Follow the datasheet. Probe takes > about 280 ms longer. The driver followed the correct procedure: Keep reset asserted until the=20 power is enabled. We've seen the chips misbehave when the power supplies ramp up=20 erratically. Keeping them in reset until the power supplies are stable=20 solves that issue, if a reset signal is available. The driver is based=20 on real experience with these chips. There is no need to wait for the internal reference startup. The=20 internal reference only affects the ADC performance, it isn't required=20 for digital communication. By the time userspace gets to use the driver,=20 those 150 ms will have passed already. We actually have 8 (or more) of these chips on a single board. If it=20 takes 8x 280 ms extra to boot such a board, it will fail to meet medical=20 specs (reboot in 5 seconds). The ADS1298 datasheet says "18" clock cycles, not "2^18". Quite a=20 difference. We would definitely have noticed if the reset timeout was=20 that far off. > ... > - A command takes 4 cycles of the device clock to decode, the minimum > reset pulse is 2 cycles, and the reset takes 18 more. These were > converted with the nominal 2.048 MHz, so a command ends after a fixed > 2 us, short of 4 cycles with an external clock below 2 MHz, which the > ADS129x allows down to 1.94 MHz. Convert them with the rate of the > clock in use. At 2.048 MHz the delays do not change. > > The clock lookup was seen to fail on a Raspberry Pi 4, with a > fixed-clock in the device tree. The power-up order was found by review > and reproduced on an emulated device only. The decode time was found > with an emulated device; it is not seen on hardware running at > 2.048 MHz. > > Fixes: 00ef7708fa60 ("iio: adc: ti-ads1298: Add driver") > Signed-off-by: Stephan Costa Barros > --- > drivers/iio/adc/ti-ads1298.c | 73 +++++++++++++++++++++++++----------- > 1 file changed, 51 insertions(+), 22 deletions(-) > > diff --git a/drivers/iio/adc/ti-ads1298.c b/drivers/iio/adc/ti-ads1298.c > index 1d32b1f47..f5965b994 100644 > --- a/drivers/iio/adc/ti-ads1298.c > +++ b/drivers/iio/adc/ti-ads1298.c > @@ -84,8 +84,12 @@ > #define ADS1298_MAX_CHANNELS 8 > #define ADS1298_BITS_PER_SAMPLE 24 > #define ADS1298_CLK_RATE_HZ 2048000 > -#define ADS1298_CLOCKS_TO_USECS(x) \ > - (DIV_ROUND_UP((x) * MICROHZ_PER_HZ, ADS1298_CLK_RATE_HZ)) > +/* A command takes 4 clock cycles to decode, before the next one may sta= rt */ > +#define ADS1298_DECODE_CLOCKS 4 > +/* Power-on reset: wait 2^18 clock cycles before the reset */ > +#define ADS1298_TPOR_CLOCKS BIT(18) > +/* Start-up time of the internal reference */ > +#define ADS1298_REF_START_UP_MS 150 > /* > * Read/write register commands require 4 clocks to decode, for speeds = above > * 2x the clock rate, this would require extra time between the command= byte and > @@ -106,6 +110,7 @@ struct ads1298_private { > struct regulator *reg_avdd; > struct regulator *reg_vref; > struct clk *clk; > + unsigned long clk_rate; > struct regmap *regmap; > struct completion completion; > struct iio_trigger *trig; > @@ -180,6 +185,12 @@ static const struct iio_chan_spec ads1298_channels[]= =3D { > ADS1298_CHAN(7), > }; > =20 > +static unsigned int ads1298_clocks_to_usecs(struct ads1298_private *priv= , > + unsigned int clocks) > +{ > + return DIV_ROUND_UP(clocks * USEC_PER_SEC, priv->clk_rate); > +} > + > static int ads1298_write_cmd(struct ads1298_private *priv, u8 command) > { > struct spi_transfer xfer =3D { > @@ -188,7 +199,7 @@ static int ads1298_write_cmd(struct ads1298_private *= priv, u8 command) > .len =3D 1, > .speed_hz =3D ADS1298_SPI_BUS_SPEED_SLOW, > .delay =3D { > - .value =3D 2, > + .value =3D ads1298_clocks_to_usecs(priv, ADS1298_DECODE_CLOCKS), > .unit =3D SPI_DELAY_UNIT_USECS, > }, > }; > @@ -433,7 +444,7 @@ static int ads1298_reg_write(void *context, unsigned = int reg, unsigned int val) > .len =3D 3, > .speed_hz =3D ADS1298_SPI_BUS_SPEED_SLOW, > .delay =3D { > - .value =3D 2, > + .value =3D ads1298_clocks_to_usecs(priv, ADS1298_DECODE_CLOCKS), > .unit =3D SPI_DELAY_UNIT_USECS, > }, > }; > @@ -454,7 +465,7 @@ static int ads1298_reg_read(void *context, unsigned i= nt reg, unsigned int *val) > .len =3D 3, > .speed_hz =3D ADS1298_SPI_BUS_SPEED_SLOW, > .delay =3D { > - .value =3D 2, > + .value =3D ads1298_clocks_to_usecs(priv, ADS1298_DECODE_CLOCKS), > .unit =3D SPI_DELAY_UNIT_USECS, > }, > }; > @@ -730,7 +741,14 @@ static int ads1298_init(struct iio_dev *indio_dev) > if (regulator_get_voltage(priv->reg_avdd) >=3D 4400000) > val |=3D ADS1298_MASK_CONFIG3_VREF_4V; > } > - return regmap_write(priv->regmap, ADS1298_REG_CONFIG3, val); > + ret =3D regmap_write(priv->regmap, ADS1298_REG_CONFIG3, val); > + if (ret) > + return ret; > + > + if (!priv->reg_vref) > + msleep(ADS1298_REF_START_UP_MS); > + > + return 0; > } > =20 > static int ads1298_probe(struct spi_device *spi) > @@ -739,6 +757,7 @@ static int ads1298_probe(struct spi_device *spi) > struct iio_dev *indio_dev; > struct device *dev =3D &spi->dev; > struct gpio_desc *reset_gpio; > + unsigned long clk_rate; > int ret; > =20 > indio_dev =3D devm_iio_device_alloc(dev, sizeof(*priv)); > @@ -753,6 +772,19 @@ static int ads1298_probe(struct spi_device *spi) > return dev_err_probe(dev, PTR_ERR(reset_gpio), > "Cannot get reset GPIO\n"); > =20 > + priv->reg_avdd =3D devm_regulator_get(dev, "avdd"); > + if (IS_ERR(priv->reg_avdd)) > + return dev_err_probe(dev, PTR_ERR(priv->reg_avdd), > + "Failed to get avdd regulator\n"); > + > + ret =3D regulator_enable(priv->reg_avdd); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to enable avdd regulator\n"); > + > + ret =3D devm_add_action_or_reset(dev, ads1298_reg_disable, priv->reg_av= dd); > + if (ret) > + return ret; > + > /* VREF can be supplied externally, otherwise use internal reference *= / > priv->reg_vref =3D devm_regulator_get_optional(dev, "vref"); > if (IS_ERR(priv->reg_vref)) { > @@ -771,22 +803,15 @@ static int ads1298_probe(struct spi_device *spi) > return ret; > } > =20 > - priv->clk =3D devm_clk_get_optional_enabled(dev, "clk"); > + /* The clock follows the supplies */ > + priv->clk =3D devm_clk_get_optional_enabled(dev, NULL); > if (IS_ERR(priv->clk)) > return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clk\n"); > =20 > - priv->reg_avdd =3D devm_regulator_get(dev, "avdd"); > - if (IS_ERR(priv->reg_avdd)) > - return dev_err_probe(dev, PTR_ERR(priv->reg_avdd), > - "Failed to get avdd regulator\n"); > - > - ret =3D regulator_enable(priv->reg_avdd); > - if (ret) > - return dev_err_probe(dev, ret, "Failed to enable avdd regulator\n"); > - > - ret =3D devm_add_action_or_reset(dev, ads1298_reg_disable, priv->reg_av= dd); > - if (ret) > - return ret; > + clk_rate =3D priv->clk ? clk_get_rate(priv->clk) : 0; > + if (!clk_rate) > + clk_rate =3D ADS1298_CLK_RATE_HZ; > + priv->clk_rate =3D clk_rate; > =20 > priv->spi =3D spi; > init_completion(&priv->completion); > @@ -800,12 +825,15 @@ static int ads1298_probe(struct spi_device *spi) > indio_dev->channels =3D ads1298_channels; > indio_dev->info =3D &ads1298_info; > =20 > + /* Power-on reset time, counted from when the clock is valid */ > + msleep(DIV_ROUND_UP(ADS1298_TPOR_CLOCKS * MILLI, clk_rate)); > + > if (reset_gpio) { > /* > * Deassert reset now that clock and power are active. > * Minimum reset pulsewidth is 2 clock cycles. > */ > - fsleep(ADS1298_CLOCKS_TO_USECS(2)); > + fsleep(ads1298_clocks_to_usecs(priv, 2)); > gpiod_set_value_cansleep(reset_gpio, 0); > } else { > ret =3D ads1298_write_cmd(priv, ADS1298_CMD_RESET); > @@ -813,7 +841,7 @@ static int ads1298_probe(struct spi_device *spi) > return dev_err_probe(dev, ret, "RESET failed\n"); > } > /* Wait 18 clock cycles for reset command to complete */ > - fsleep(ADS1298_CLOCKS_TO_USECS(18)); > + fsleep(ads1298_clocks_to_usecs(priv, 18)); > =20 > ret =3D ads1298_init(indio_dev); > if (ret) > @@ -824,7 +852,8 @@ static int ads1298_probe(struct spi_device *spi) > priv->rdata_xfer.rx_buf =3D priv->rx_buffer; > priv->rdata_xfer.len =3D ADS1298_SPI_RDATA_BUFFER_SIZE(indio_dev->num_= channels); > /* Must keep CS low for 4 clocks */ > - priv->rdata_xfer.delay.value =3D 2; > + priv->rdata_xfer.delay.value =3D ads1298_clocks_to_usecs(priv, > + ADS1298_DECODE_CLOCKS); > priv->rdata_xfer.delay.unit =3D SPI_DELAY_UNIT_USECS; > spi_message_init_with_transfers(&priv->rdata_msg, &priv->rdata_xfer, 1= ); > priv->rdata_msg.complete =3D &ads1298_rdata_complete; --=20 Mike Looijmans System Expert TOPIC Embedded Products B.V. Materiaalweg 4, 5681 RJ Best The Netherlands T: +31 (0) 499 33 69 69 E: mike.looijmans@topic.nl W: www.topic.nl