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([2a02:810d:15c0:828:77d1:16a1:abe1:84fc]) by smtp.gmail.com with ESMTPSA id u18-20020a170906069200b00967004187b8sm10843538ejb.36.2023.05.16.05.56.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 May 2023 05:56:48 -0700 (PDT) Message-ID: <1853f049-4f00-b7f0-973a-2c4e7b0b2634@linaro.org> Date: Tue, 16 May 2023 14:56:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v2 1/2] dt-bindings: phy: add mediatek mipi csi driver v 0.5 To: Julien Stephan Cc: robh@kernel.org, chunkuang.hu@kernel.org, linux-mediatek@lists.infradead.org, Florian Sylvestre , Chunfeng Yun , Andy Hsieh , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , "moderated list:ARM/Mediatek USB3 PHY DRIVER" , "open list:GENERIC PHY FRAMEWORK" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list References: <20230515090551.1251389-1-jstephan@baylibre.com> <20230515090551.1251389-2-jstephan@baylibre.com> <4yppinkucchwnwtnnpbqdn4bejmntjq3q6mx6es55f2pwyce3c@qdhdks47lpyt> Content-Language: en-US From: Krzysztof Kozlowski In-Reply-To: <4yppinkucchwnwtnnpbqdn4bejmntjq3q6mx6es55f2pwyce3c@qdhdks47lpyt> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/05/2023 11:41, Julien Stephan wrote: > On Tue, May 16, 2023 at 10:07:47AM +0200, Krzysztof Kozlowski wrote: >> On 15/05/2023 11:05, Julien Stephan wrote: >>> From: Florian Sylvestre >>> >>> This adds the bindings, for the MIPI CD-PHY module v 0.5 embedded in >>> some Mediatek soc, such as the mt8365 >>> >>> Signed-off-by: Florian Sylvestre >>> Signed-off-by: Julien Stephan >> >> What are the changes? IOW: changelog here or in cover letter. >> > Hi Krzysztof, > I added a changelog in the cover letter, but I will try to be more > descritpive next time. Changes from v1 are mainly style issues fixed > (mostly from your first review) What do you mean by "in cover letter"? There is no cover letter. > >> Subject: you have some multiple spaces. >> >> Subject: drop driver. Bindings are not for drivers. >> >>> --- >>> .../phy/mediatek,phy-mipi-csi-0-5.yaml | 62 +++++++++++++++++++ >>> MAINTAINERS | 6 ++ >>> 2 files changed, 68 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,phy-mipi-csi-0-5.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/phy/mediatek,phy-mipi-csi-0-5.yaml b/Documentation/devicetree/bindings/phy/mediatek,phy-mipi-csi-0-5.yaml >>> new file mode 100644 >>> index 000000000000..5aa8c0b41cdf >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/phy/mediatek,phy-mipi-csi-0-5.yaml >>> @@ -0,0 +1,62 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-Only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/phy/mediatek,phy-mipi-csi-0-5.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Mediatek Sensor Interface MIPI CSI CD-PHY >>> + >>> +maintainers: >>> + - Julien Stephan >>> + - Andy Hsieh >>> + >>> +description: >>> + The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2 >>> + receivers. The number of PHYs depends on the SoC model. >>> + Depending on the soc model, each PHYs can support CDPHY or DPHY only >>> + >>> +properties: >>> + compatible: >>> + enum: >>> + - mediatek,phy-mipi-csi-0-5 >> >> SoC based compatibles. 0-5 is odd. >> >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + '#phy-cells': >>> + const: 0 >>> + >>> + mediatek,is_cdphy: >> >> No underscores in node names. >> >>> + description: >>> + Specify if the current phy support CDPHY configuration >> >> Why this cannot be implied from compatible? Add specific compatibles. >> >> > This cannot be implied by compatible because the number of phys depends > on the soc and each phy can be either D-PHY only or CD-PHY capable. > For example mt8365 has 2 phy: CSI0 and CSI1. CSI1 is DPHY only and CSI0 is CD-PHY So it is SoC specific so why it cannot be implied by compatible? I don't understand. You will have SoC specific compatibles, right? or you just ignored my comments here? >> Best regards, Krzysztof