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From: "Moger, Babu" <babu.moger@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: tglx@linutronix.de, mingo@redhat.com,
	dave.hansen@linux.intel.com, hpa@zytor.com, pbonzini@redhat.com,
	seanjc@google.com, vkuznets@redhat.com, jmattson@google.com,
	joro@8bytes.org, wanpengli@tencent.com,
	linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
	x86@kernel.org
Subject: Re: [PATCH v2 1/2] x86/cpufeatures: Add virtual TSC_AUX feature bit
Date: Wed, 20 Apr 2022 10:02:21 -0500	[thread overview]
Message-ID: <186da20a-c4a2-98a1-1027-7b4390bf8cf2@amd.com> (raw)
In-Reply-To: <Yl/x2kpQeKylIyPb@zn.tnic>


On 4/20/22 06:43, Borislav Petkov wrote:
> On Tue, Apr 19, 2022 at 03:53:52PM -0500, Babu Moger wrote:
>> The TSC_AUX Virtualization feature allows AMD SEV-ES guests to securely use
>> TSC_AUX (auxiliary time stamp counter data) MSR in RDTSCP and RDPID
>> instructions.
>>
>> The TSC_AUX MSR is typically initialized to APIC ID or another unique
>> identifier so that software can quickly associate returned TSC value
>> with the logical processor.
>>
>> Add the feature bit and also include it in the kvm for detection.
>>
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>> Acked-by: Borislav Petkov <bp@suse.de>
>> ---
>> v2:
>> Fixed the text(commented by Boris).
>> Added Acked-by from Boris.
>>
>> v1:
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fkvm%2F164937947020.1047063.14919887750944564032.stgit%40bmoger-ubuntu%2F&amp;data=05%7C01%7Cbabu.moger%40amd.com%7Cf826192970c549ae73af08da22c2ff93%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637860518176768607%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=fExIt5ghvuew%2BXKzGyixye2%2BLQncv91274nt8I0NXbY%3D&amp;reserved=0
>>
>>  arch/x86/include/asm/cpufeatures.h |    1 +
>>  arch/x86/kvm/cpuid.c               |    2 +-
>>  2 files changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index 73e643ae94b6..1bc66a17a95a 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -405,6 +405,7 @@
>>  #define X86_FEATURE_SEV			(19*32+ 1) /* AMD Secure Encrypted Virtualization */
>>  #define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* "" VM Page Flush MSR is supported */
>>  #define X86_FEATURE_SEV_ES		(19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
>> +#define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* Virtual TSC_AUX */
> I forgot from the last time: nothing is going to use that bit in
> userspace so make that
>
> #define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* "" Virtual TSC_AUX */

Ok. Sure.

Thanks

>
> please.
>
> Thx.
>
-- 
Thanks
Babu Moger


  reply	other threads:[~2022-04-20 15:03 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-19 20:53 Babu Moger
2022-04-19 20:54 ` [PATCH v2 2/2] KVM: SVM: Disable RDTSCP and TSC_AUX MSR intercepts when V_TSC_AUX is present Babu Moger
2022-04-20 11:43 ` [PATCH v2 1/2] x86/cpufeatures: Add virtual TSC_AUX feature bit Borislav Petkov
2022-04-20 15:02   ` Moger, Babu [this message]
2022-04-20 16:27 ` Paolo Bonzini

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