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> } > > +static void sdhci_gl9767_uhs2_phy_reset_assert(struct sdhci_host *host) > +{ > + struct sdhci_pci_slot *slot = sdhci_priv(host); > + struct pci_dev *pdev = slot->chip->pdev; > + u32 value; > + > + gl9767_vhs_write(pdev); > + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); > + value |= PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN; > + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); > + value &= ~PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; > + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); > + gl9767_vhs_read(pdev); > +} > + > +static void sdhci_gl9767_uhs2_phy_reset_deassert(struct sdhci_host *host) > +{ > + struct sdhci_pci_slot *slot = sdhci_priv(host); > + struct pci_dev *pdev = slot->chip->pdev; > + u32 value; > + > + gl9767_vhs_write(pdev); > + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); > + value |= PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; Maybe add a small comment about PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE and PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN being updated separately. > + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); > + value &= ~PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN; > + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); > + gl9767_vhs_read(pdev); > +} sdhci_gl9767_uhs2_phy_reset_assert() and sdhci_gl9767_uhs2_phy_reset_deassert() are fairly similar. Maybe consider: static void sdhci_gl9767_uhs2_phy_reset(struct sdhci_host *host, bool assert) { struct sdhci_pci_slot *slot = sdhci_priv(host); struct pci_dev *pdev = slot->chip->pdev; u32 value, set, clr; if (assert) { set = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN; clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; } else { set = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN; } gl9767_vhs_write(pdev); pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); value |= set; pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); value &= ~clr; pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); gl9767_vhs_read(pdev); } > + > +static void __gl9767_uhs2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) > +{ > + u8 pwr = 0; > + > + if (mode != MMC_POWER_OFF) { > + pwr = sdhci_get_vdd_value(vdd); > + if (!pwr) > + WARN(1, "%s: Invalid vdd %#x\n", > + mmc_hostname(host->mmc), vdd); > + pwr |= SDHCI_VDD2_POWER_180; > + } > + > + if (host->pwr == pwr) > + return; > + > + host->pwr = pwr; > + > + if (pwr == 0) { > + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); > + } else { > + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); > + > + pwr |= SDHCI_POWER_ON; > + sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); > + mdelay(5); Can be mmc_delay(5) > + > + sdhci_gl9767_uhs2_phy_reset_assert(host); > + pwr |= SDHCI_VDD2_POWER_ON; > + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); > + mdelay(5); Can be mmc_delay(5) > + } > +} > + > static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock) > { > struct sdhci_pci_slot *slot = sdhci_priv(host); > @@ -1205,6 +1270,10 @@ static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock) > } > > sdhci_enable_clk(host, clk); > + > + if (mmc_card_uhs2(host->mmc)) > + sdhci_gl9767_uhs2_phy_reset_deassert(host); > + > gl9767_set_low_power_negotiation(pdev, true); > } > > @@ -1476,7 +1545,7 @@ static void sdhci_gl9767_set_power(struct sdhci_host *host, unsigned char mode, > gl9767_vhs_read(pdev); > > sdhci_gli_overcurrent_event_enable(host, false); > - sdhci_uhs2_set_power(host, mode, vdd); > + __gl9767_uhs2_set_power(host, mode, vdd); > sdhci_gli_overcurrent_event_enable(host, true); > } else { > gl9767_vhs_write(pdev);