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No OS-level knob found In-Reply-To: <18b4f7b23ba6392f.e25301f473da0264.54f7bc72d1817dd4@GordonMsi> References: 18b4e4f7089aa4f1.da8dbe994ae3bb77.445e21b98b0b205b@GordonMsi 78ebe71f-85a8-4675-aa0e-6011353dee39@linux.intel.com 18b4f7b23ba6392f.e25301f473da0264.54f7bc72d1817dd4@GordonMsi Message-ID: <18b4f8f0c2ce37be.8d4c4c4ee804b95a.4c2042ec04b99872@GordonMsi> Date: Mon, 1 Jun 2026 13:44:25 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Hi all, A quick correction and a sharper question after probing the PCIe side. I checked the controller's PCIe config (lspci -vvv): the xHC function (0000:6b:00.3) has no Latency Tolerance Reporting extended capability at all and reports DevCap2 LTR-. Its upstream root port (00:08.1) is LTR- as well. So the PCIe-layer variant I floated in my last mail is a dead end -- there is no LTR register to write, and neither the endpoint nor the root port advertises the mechanism. That leaves an apparent contradiction I'd appreciate help squaring: - USB/xHCI layer: HCCPARAMS1 LTC = 1 (the controller advertises Latency Tolerance Messaging Capability). - PCIe layer: the same function is LTR- (no LTR capability at all). So if I issue a Set LTV command (the driver-injected path you mentioned), where does the xHC actually forward that aggregated tolerance value to the fabric, given it has no PCIe LTR egress? Is there an internal sideband path to the DF on these integrated AMD controllers, or does LTC only affect USB link power states on this silicon -- in which case Set LTV would never reach the Data Fabric? If it's an internal/sideband path (Mario / Shyam?), a Set LTV PoC is still worth trying. If LTC is purely USB-link-scoped here, it won't touch the DF idle problem and I should look elsewhere. That distinction decides whether I write the PoC at all. Thanks, Gordon Chen