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Mon, 26 Oct 2026 09:00:51 +0800 (CST) Received: from [10.67.110.36] (unknown [10.67.110.36]) by APP2 (Coremail) with UTF8SMTPA id Syh0CgDHletBpt5qDS1SBw--.17922S2; Mon, 26 Oct 2026 09:00:50 +0800 (CST) Message-ID: <18c1e63e-bdfd-4e74-bda6-61b68c915c0c@huaweicloud.com> Date: Mon, 26 Oct 2026 09:00:49 +0800 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 00/15] perf annotate arm64: Support instruction tracking for data type profiling To: Arnaldo Carvalho de Melo Cc: Namhyung Kim , james.clark@linaro.org, xueshuai@linux.alibaba.com, Peter Zijlstra , leo.yan@linux.dev, Li Huafei , Ian Rogers , Kim Phillips , Mark Rutland , Ingo Molnar , Bill Wendling , Nick Desaulniers , Alexander Shishkin , Adrian Hunter , Zecheng Li , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev References: <18de9e8f-3709-4bc9-b11b-3813e1ba98b7@huaweicloud.com> Content-Language: en-US From: Tengda Wu In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CM-TRANSID:Syh0CgDHletBpt5qDS1SBw--.17922S2 X-Coremail-Antispam: 1UD129KBjvJXoWxAFy3Xw4UAr4UJF4fWFyfJFb_yoW5AFykpr Z5Ca1rtFWDJr40yFsFqw47Xr4aga1rWr47Wrn5t34SkFn0vFn3tFs3K3W5WFZ3Cr15Cr17 Xw4jvF93Zw4jvFDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUvFb4IE77IF4wAFF20E14v26ryj6rWUM7CY07I20VC2zVCF04k2 6cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4 vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7Cj xVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x 0267AKxVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02 F40Ex7xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4I kC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41lFIxGxcIEc7CjxVA2Y2ka0xkIwI1lc7CjxVAa w2AFwI0_GFv_Wryl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxV Aqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a 6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6x kF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvj xUIa0PDUUUU X-CM-SenderInfo: pzxwv0hjgdqx5xdzvxpfor3voofrz/ On 2026/10/24 5:10, Arnaldo Carvalho de Melo wrote: > On Wed, Oct 21, 2026 at 10:25:40AM +0800, Tengda Wu wrote: >> Hi, >> >> On 2026/10/20 21:44, Tengda Wu wrote: >>> This series adds arm64 support to perf's data type profiling by >>> implementing instruction tracking for the arm64 architecture. >>> >>> The main changes since v7 include: >>> v7: https://lore.kernel.org/all/cover.1791629326.git.wutengda@huaweicloud.com/ >>> >>> * Patch 02: Minor optimizations to update_insn_state_arm64 to facilitate >>> future extension, including: >>> - Encapsulating call instruction handling into update_call_insn_state() >>> - Encapsulating invalidate dst regs handling into invalidate_unhandled_insn_regs() >>> - Renaming is_readonly_branch_or_cmp() to is_readonly_insn() >>> No functional changes. >>> >>> * Fix issues raised by Sashiko: >>> - Patch 06: Complete the status register invalidation logic for >>> exclusive stores. >>> - Patch 13 & 15: Complete the lifetime invalidation logic for adrp >>> and mrs instructions. >>> Regarding the status register invalidation issue for instructions >>> such as cas/swp as well, we plan to support this incrementally >>> after the relevant instructions are refined; this patch temporarily >>> ignores and does not handle it (a TODO marker has already been >>> reserved in patch 02) >>> >>> Patch organization >>> ================== >>> >>> Patches 1-3: Shared infrastructure. Extract invalidate_reg_state() as >>> a common helper, add the arch_get_reg_offset() helper for >>> computing operand base offsets, and wire up the arm64 >>> entry points (arch_supports_insn_tracking(), >>> init_type_state(), and update_insn_state_arm64()). >>> >>> Patches 4-6: Core instruction tracking for arm64: function return >>> types after calls, load instructions (ldr/ldp and their >>> addressing modes), and store instructions (str/stp). >>> >>> Patches 7-9: Shared data structure improvements and an x86 fix. >>> Expand type_state_reg.imm_value to u64 so 64-bit >>> addresses can be tracked, preserve imm_value for stack >>> variables, and delete stale stack state on store of an >>> untracked register on x86. >>> >>> Patches 10-15: Remaining arm64 patterns: stack variable tracking, >>> 'mov' (register and immediate forms), 'add' member >>> address calculation, 'adrp' global variable tracking, >>> per-cpu variable access, and 'mrs sp_el0' to resolve the >>> 'current' pointer. >>> >> >> Just a quick note that this version of the patch series has addressed or >> clarified all the Sashiko review comments. I would appreciate it if you >> could take a look when you get a chance. > > Merged now, test built and pushed to perf-tools-next/perf-tools-next for > further build testing with linux-next, early next week I intend to push > it out to Linus for 7.4. > > - Arnaldo Thanks a lot for the merge and for running the build tests. Much appreciated! Best regards, Tengda