From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE835158871; Wed, 24 Jul 2024 10:12:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721815928; cv=none; b=Up68s+FDJpmWBxrbhnoylmrHu/B6GlNJGqxZCZBK09tftMEPqeUI2Gcf1MrGh6T9fkJXc5zr6yQUS/VKpKPv2YVjOL0ic+xeaoeNmKMiE+6q5N38g6Y3daZyM43vkFTOHX6qL2UFXp/UVEnlAHY5EPDOTHvNO8GOqxoBciS6RZE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721815928; c=relaxed/simple; bh=Uqbvr11D9AdAvRrO/Gx+qH47OKL06kpUfqsqfplLr44=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=YOI9iqqHv/NjQWinHZ4LQKGcRmkqGPnV2HJAumFJhfxBNmSov08xnxIIgM+Jv4OKs4y3fDADw2m+PaWmQ5zuXRE7Ghh49tVTHY0WctEOoO2NTT4mXhbKMJi6EjE6cd3cNCHqbJeXnsspcOeJ3RfVfLqVJVQrqyg6qyYuXjS4hco= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AyhsA9nH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AyhsA9nH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4C163C4AF0C; Wed, 24 Jul 2024 10:12:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721815928; bh=Uqbvr11D9AdAvRrO/Gx+qH47OKL06kpUfqsqfplLr44=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=AyhsA9nHW5INzi1KByBWIblUwgL59r4vkjiK5TJdPIP4Y+QGqwnJmudUSFfb4v+2K DvD5MgWjcYh1RlxhAuwUiwaPOF1tATyEOteGpUFM5OIsTpTUpUU7j0WjTVJyU+ValF ZVWQYlLTNHcjH8xITeWv0rRZ80shTwkkZOcpScL3wb+j+R++Smx9qER+XT0fTy1Gq6 3cFNwVwWt56RkVAkCp8S2d2CTwAIe+O6lPE2r0vh/WkfQiHC5OBMRYUlUBK0InkkwQ 5R8AHESTtcWQty8ShWW2G7kVRYVmHrShUU0oGeKqoOqrarOAO9DfPToh83OZHiPQ1X cBWYgcrdSBASQ== Message-ID: <18f5565f-11f5-49ce-a816-366cff25b703@kernel.org> Date: Wed, 24 Jul 2024 12:12:03 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/4] dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings To: Sunyeal Hong , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20240722223333.1137947-1-sunyeal.hong@samsung.com> <20240722223333.1137947-2-sunyeal.hong@samsung.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 23/07/2024 00:33, Sunyeal Hong wrote: > Add dt-schema for ExynosAuto v920 SoC clock controller. > Add device tree clock binding definitions for below CMU blocks. > > - CMU_TOP > - CMU_PERIC0 > > Signed-off-by: Sunyeal Hong > --- > .../clock/samsung,exynosautov920-clock.yaml | 115 +++++++++++ > .../clock/samsung,exynosautov920.h | 191 ++++++++++++++++++ > 2 files changed, 306 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml > create mode 100644 include/dt-bindings/clock/samsung,exynosautov920.h > > diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml > new file mode 100644 > index 000000000000..90f9f17da959 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml > @@ -0,0 +1,115 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Samsung ExynosAuto v920 SoC clock controller > + > +maintainers: > + - Sunyeal Hong > + - Chanwoo Choi > + - Krzysztof Kozlowski > + - Sylwester Nawrocki > + > +description: | > + ExynosAuto v920 clock controller is comprised of several CMU units, generating > + clocks for different domains. Those CMU units are modeled as separate device > + tree nodes, and might depend on each other. Root clocks in that clock tree are > + two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz). > + The external OSCCLK must be defined as fixed-rate clock in dts. > + > + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and > + dividers; all other clocks of function blocks (other CMUs) are usually > + derived from CMU_TOP. > + > + Each clock is assigned an identifier and client nodes can use this identifier > + to specify the clock which they consume. All clocks available for usage > + in clock consumer nodes are defined as preprocessor macros in > + 'include/dt-bindings/clock/samsung,exynosautov920.h' header. > + > +properties: > + compatible: > + enum: > + - samsung,exynosautov920-cmu-top > + - samsung,exynosautov920-cmu-peric0 > + > + clocks: > + minItems: 1 > + maxItems: 3 > + > + clock-names: > + minItems: 1 > + maxItems: 3 > + > + "#clock-cells": > + const: 1 > + > + reg: > + maxItems: 1 > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: samsung,exynosautov920-cmu-top > + > + then: > + properties: > + clocks: > + items: > + - description: External reference clock (38.4 MHz) > + > + clock-names: > + items: > + - const: oscclk > + > + - if: > + properties: > + compatible: > + contains: > + const: samsung,exynosautov920-cmu-peric0 > + > + then: > + properties: > + clocks: > + items: > + - description: External reference clock (38.4 MHz) > + - description: CMU_PERIC0 NOC clock (from CMU_TOP) > + - description: CMU_PERIC0 IP clock (from CMU_TOP) > + > + clock-names: > + items: > + - const: oscclk > + - const: noc > + - const: ip > + > +required: > + - compatible > + - "#clock-cells" > + - clocks > + - clock-names > + - reg > + > +additionalProperties: false > + > +examples: > + # Clock controller node for CMU_PERIC0 > + - | > + #include > + > + cmu_peric0: clock-controller@10800000 { > + compatible = "samsung,exynosautov920-cmu-peric0"; > + reg = <0x10800000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&xtcxo>, > + <&cmu_top DOUT_CLKCMU_PERIC0_NOC>, > + <&cmu_top DOUT_CLKCMU_PERIC0_IP>; > + clock-names = "oscclk", > + "noc", > + "ip"; > + }; > + > +... > diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h > new file mode 100644 > index 000000000000..ad89728a4396 > --- /dev/null > +++ b/include/dt-bindings/clock/samsung,exynosautov920.h > @@ -0,0 +1,191 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2024 Samsung Electronics Co., Ltd. > + * Author: Sunyeal Hong > + * > + * Device Tree binding constants for ExynosAuto v920 clock controller. > + */ > + > +#ifndef _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H > +#define _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H > + > +/* CMU_TOP */ > +#define FOUT_SHARED0_PLL 1 > +#define FOUT_SHARED1_PLL 2 > +#define FOUT_SHARED2_PLL 3 > +#define FOUT_SHARED3_PLL 4 > +#define FOUT_SHARED4_PLL 5 > +#define FOUT_SHARED5_PLL 6 > +#define FOUT_MMC_PLL 7 > + > +/* MUX in CMU_TOP */ > +#define MOUT_SHARED0_PLL 101 This is some odd numbering. Numbers start from 0 or 1 and are continuous. Best regards, Krzysztof