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Mon, 21 Apr 2025 07:02:15 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 21 Apr 2025 07:02:14 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 21 Apr 2025 07:02:14 -0500 Received: from [10.24.72.182] (jayesh-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.72.182]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53LC2B4g006706; Mon, 21 Apr 2025 07:02:11 -0500 Message-ID: <18ff4046-34fa-48bf-a1e8-3472de46ac01@ti.com> Date: Mon, 21 Apr 2025 17:32:10 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/7] arm64: dts: ti: k3-j721s2-common-proc-board: Enable DisplayPort-1 To: "Kumar, Udit" , , , , CC: , , , , , References: <20250411105155.303657-1-j-choudhary@ti.com> <20250411105155.303657-7-j-choudhary@ti.com> <945e0247-a971-48de-adb1-60a1e7fe5f24@ti.com> Content-Language: en-US From: Jayesh Choudhary In-Reply-To: <945e0247-a971-48de-adb1-60a1e7fe5f24@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Hello Udit, On 19/04/25 14:59, Kumar, Udit wrote: > > On 4/11/2025 4:21 PM, Jayesh Choudhary wrote: >> Enable DSI display for J721S2 EVM. >> >> Add the endpoint nodes to describe connection from: >> DSS => DSI Bridge => DSI to eDP bridge => DisplayPort-1 >> >> Set status for all required nodes for DisplayPort-1 as 'okay'. >> >> Signed-off-by: Jayesh Choudhary >> --- >>   .../dts/ti/k3-j721s2-common-proc-board.dts    | 95 +++++++++++++++++++ >>   1 file changed, 95 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts >> b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts >> index f691ae4c19e6..15a7d9b813d3 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts >> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts >> @@ -93,6 +93,29 @@ vdd_sd_dv: gpio-regulator-TLV71033 { >>                <3300000 0x1>; >>       }; >> [..] >> + >> +&dss { >> +    /* >> +     * These clock assignments are chosen to enable the following >> outputs: >> +     * >> +     * VP0 - DisplayPort SST >> +     * VP1 - DPI0 >> +     * VP2 - DSI >> +     * VP3 - DPI1 >> +     */ > > Sorry for basic question,  In this series , you are enabling only DSI > interface. > > why you need clocking for other interfaces ? > We do not need them. We only need clockID 14 with its parent clock as 16 (which is not the selected parent by default) The other display on the EVM (MHDP on DP-0) will consume clockID 2 whose default parent selection is okay. I will change this. Thanks, Jayesh > >> +    status = "okay"; >> [..]