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Wed, 11 Dec 2019 17:30:01 +0000 From: Mihail Atanassov To: "james qian wang (Arm Technology China)" CC: nd , "Jonathan Chai (Arm Technology China)" , "Lowry Li (Arm Technology China)" , "Tiannan Zhu (Arm Technology China)" , nd , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , Ben Davis , "Oscar Zhang (Arm Technology China)" , "Channing Chen (Arm Technology China)" Subject: Re: [PATCH] drm/komeda: Correct d71 register block counting Thread-Topic: [PATCH] drm/komeda: Correct d71 register block counting Thread-Index: AQHVryCISCrm/Iio6km6+MdLrsMXu6e1I3uA Date: Wed, 11 Dec 2019 17:30:01 +0000 Message-ID: <1904852.g9mvNTCQN0@e123338-lin> References: <20191210061015.25905-1-james.qian.wang@arm.com> In-Reply-To: <20191210061015.25905-1-james.qian.wang@arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [217.140.106.54] x-clientproxiedby: LO2P265CA0194.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:9e::14) To VI1PR08MB4078.eurprd08.prod.outlook.com (2603:10a6:803:e5::28) Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Mihail.Atanassov@arm.com; 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X-MS-Office365-Filtering-Correlation-Id-Prvs: ec7f7202-3695-4c4e-534f-08d77e5fc042 NoDisclaimer: True X-Forefront-PRVS: 024847EE92 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Q1yXfaTnmF/TM4XgHymVoxQJaaa+PqArkfH0nZOxDXNFSvunprne31eY8gOKFcVsW5NffZ+QqfkaCyzEBK+ggnL8tcWrrXh4zC3YjEWrS1aI7Ip9TXwlfUP+cmAqkSRy6GV784bmqDoolsBujGu/b7ZSBzvi2hp2lKAhj0MeipgWb3VSELRpwpZnQOKT7vuCVrS593uAh1Mjreptspqv/v3NwSimlJ9ftJyT5bvrdVhnAkaoU7dSB3jpHvWt6+613BHrqWyDzu6i92uQGGAoQbMDTxyTJD32q+UvvvIPmephIBJKbwO3ZJj243OeKG0w8H0OGL6yMGKPq8pmdrP+bO7mS7SeGoiE5Cvs4h4cQvYQwapIwTRiRnH0vg1SgSxkBDfS52kXn5jvbnr4U5TOpDMDdHGIbhVds5cveYn4AuRALvAM4GLF6ojX3y7QMxzwSGQHp6wBH4jigalQwolYZpFN2foEVCPg9idBeGeXiBKmxfB6Fk0C2eVyupfh+Cik X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2019 17:30:10.5849 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 852f9bb7-859f-4dab-4c4a-08d77e5fc61c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0801MB1882 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday, 10 December 2019 06:10:34 GMT james qian wang (Arm Technology C= hina) wrote: > Per HW, d71->num_blocks includes reserved blocks but no PERIPH block, > correct the block counting accordingly. > D71 happens to only have one reserved block and periph block, which > hides this counting error. >=20 > Signed-off-by: james qian wang (Arm Technology China) > --- > drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c b/drivers/g= pu/drm/arm/display/komeda/d71/d71_dev.c > index 822b23a1ce75..d53f95dea0a1 100644 > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c > @@ -414,8 +414,11 @@ static int d71_enum_resources(struct komeda_dev *mde= v) > d71->pipes[i] =3D to_d71_pipeline(pipe); > } > =20 > - /* loop the register blks and probe */ > - i =3D 2; /* exclude GCU and PERIPH */ > + /* loop the register blks and probe. > + * NOTE: d71->num_blocks includes reserved blocks. > + * d71->num_blocks =3D GCU + valid blocks + reserved blocks > + */ > + i =3D 1; /* exclude GCU */ > offset =3D D71_BLOCK_SIZE; /* skip GCU */ > while (i < d71->num_blocks) { > blk_base =3D mdev->reg_base + (offset >> 2); > @@ -425,9 +428,9 @@ static int d71_enum_resources(struct komeda_dev *mdev= ) > err =3D d71_probe_block(d71, &blk, blk_base); > if (err) > goto err_cleanup; > - i++; > } > =20 > + i++; > offset +=3D D71_BLOCK_SIZE; > } > =20 >=20 Reviewed-by: Mihail Atanassov --=20 Mihail