From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752644AbbJENLO (ORCPT ); Mon, 5 Oct 2015 09:11:14 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:56871 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752497AbbJENLJ (ORCPT ); Mon, 5 Oct 2015 09:11:09 -0400 X-AuditID: cbfee68d-f79ae6d00000149a-6c-561276e07187 Date: Mon, 05 Oct 2015 13:10:55 +0000 (GMT) From: Sarbojit Ganguly Subject: Re: Re: [PATCH v2] arm: Adding support for atomic half word exchange To: Will Deacon , Sarbojit Ganguly Cc: "linux@arm.linux.org.uk" , "catalin.marinas@arm.com" , "Waiman.Long@hp.com" , "peterz@infradead.org" , VIKRAM MUPPARTHI , "linux-kernel@vger.kernel.org" , SUNEEL KUMAR SURIMANI , SHARAN ALLUR , "torvalds@linux-foundation.org" , "linux-arm-kernel@lists.infradead.org" Reply-to: ganguly.s@samsung.com MIME-version: 1.0 X-MTR: 20151005130620070@ganguly.s Msgkey: 20151005130620070@ganguly.s X-EPLocale: en_US.windows-1252 X-Priority: 3 X-EPWebmail-Msg-Type: personal X-EPWebmail-Reply-Demand: 0 X-EPApproval-Locale: X-EPHeader: ML X-MLAttribute: X-RootMTR: 20151005130620070@ganguly.s X-ParentMTR: X-ArchiveUser: X-CPGSPASS: Y X-ConfirmMail: N,general Content-type: text/plain; charset=windows-1252 MIME-version: 1.0 Message-id: <1912649938.590071444050653292.JavaMail.weblogic@epmlwas01c> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMIsWRmVeSWpSXmKPExsWyRsSkVvdBmVCYwbpjbBaXd81hc2D0+LxJ LoAxissmJTUnsyy1SN8ugSvj1yuxgh7Jiu0dM5kbGLdIdDFycAgJqEj0TYroYuTkkBAwkWj/ foQNwhaTuHBvPZDNBVSylFGidfNnJpB6kKLNMwUg4nMYJT7u/MkE0sACNOf/3b+MIDabgL7E 6f0vweLCAr4S+zvPsYLYIgKhEos/7GAHaWYWWMkiMf3jMWaQhJCAvET7i+1gDbwCghInZz5h gbhCSeLI9oMsIIt5BZQl/j+qhQjLSSyZepkJwuaVmNH+lAUmPu3rGmYIW1ri/KwNjDDPLP7+ GCrOL3Hs9g6oXgGJqWcOQtWoS/Tt/Qn1PJ/EmoVvWWDqd51azgyzq2Hjb3YIW0Jia8sTsL+Y BRQlpnQ/ZIewDSSOLJrDiu4VXgEPicmdK1lAfpcQmMohMXX5TJYJjEqzkNTNQjJrFpJZyGoW MLKsYhRNLUguKE5KLzLUK07MLS7NS9dLzs/dxAhMC6f/PevdwXj7gPUhRgEORiUeXokkwTAh 1sSy4srcQ4ymwHiayCwlmpwPTD55JfGGxmZGFqYmpsZG5pZmSuK8ilI/g4UE0hNLUrNTUwtS i+KLSnNSiw8xMnFwSjUw5k2pnzh1a/yt/W9tqheqP3ilcebsETlB5bxoPWdJ/gl1PMv3ndh5 nKVMKTdRwPLaSlv5latZz72MvVVl33KYe2OJ8WGxC89sPzs9TLhwdWn2xrKqqZ2O+3fPOPVs yt+CW2f79Q5mr/I2lj9wNGQr1ySbrZdCnb/PeV6T/OaJErPVVb4Xdyvf8SmxFGckGmoxFxUn AgDRC3a/BgMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMKsWRmVeSWpSXmKPExsVy+t/tft0HZUJhBh/lLC7vmsPmwOjxeZNc AGNUmk1GamJKapFCal5yfkpmXrqtkndwvHO8qZmBoa6hpYW5kkJeYm6qrZKLT4CuW2YO0Ewl hbLEnFKgUEBicbGSvp1NUX5pSapCRn5xia1StKG5kZ6RgZ6pkZ6haayVoYGBkSlQTUJaxq9X YgU9khXbO2YyNzBukehi5OAQElCR6JsUAWJKCJhIbJ4p0MXICWSKSVy4t56ti5ELqGIOo8TH nT+ZQBIsQOX/7/5lBLHZBPQlTu9/CRYXFvCV2N95jhXEFhEIlVj8YQc7SDOzwEoWiekfjzGD JIQE5CXaX2wHa+AVEJQ4OfMJC8Q2JYkj2w+ygBzBK6As8f9RLURYTmLJ1MtMEDavxIz2pyww 8Wlf1zBD2NIS52dtYIQ5evH3x1Bxfoljt3dA9QpITD1zEKpGXaJv7082CJtPYs3Ctyww9btO LWeG2dWw8Tc7hC0hsbXlCdhfzAKKElO6H7JD2AYSRxbNYUX3Cq+Ah8TkzpUsExhlZyFJzULS PgtJO7KaBYwsqxhFUwuSC4qT0iuM9YoTc4tL89L1kvNzNzGCE9CzxTsY/5+3PsQowMGoxMMr kSQYJsSaWFZcmXuIUYKDWUmE19JVKEyINyWxsiq1KD++qDQntfgQoykw1iYyS4km5wOTY15J vKGxibmpsamFgaG5uZmSOO+NvQxhQgLpiSWp2ampBalFMH1MHJxSDYxJh/L2sb3lS/y2suQt n/fhq3m3rwVsrGmcf6993sr1a7kdvPwaI5rYelfWvpglkC9RZNK93tf8MQOv70n+9QUTYiuU xC59MtMVixc8qlAYLDvd8NrmhxkJb5cv070t9YZ5tclpBqf7p275pjeXHwjdtND+7MImtgW2 7zbV3j0meut/usunH1uVWIozEg21mIuKEwFkRSV0VgMAAA== DLP-Filter: Pass X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id t95DBJRH007140 Hello Will, My sincere apologies for the format issue. This was due to the e-mail editor which reformats the text. I am reposting the patch, please let me know if it is ok this time. v1-->v2 : Extended the guard code to cover the byte exchange case as well following opinion of Will Deacon. Checkpatch has been run and issues were taken care of. Since support for half-word atomic exchange was not there and Qspinlock on ARM requires it, modified __xchg() to add support for that as well. ARMv6 and lower does not support ldrex{b,h} so, added a guard code to prevent build breaks. Signed-off-by: Sarbojit Ganguly --- arch/arm/include/asm/cmpxchg.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 916a274..a53cbeb 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size switch (size) { #if __LINUX_ARM_ARCH__ >= 6 +#if !defined(CONFIG_CPU_V6) case 1: asm volatile("@ __xchg1\n" "1: ldrexb %0, [%3]\n" @@ -49,6 +50,22 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size : "r" (x), "r" (ptr) : "memory", "cc"); break; + + /* + * Half-word atomic exchange, required + * for Qspinlock support on ARM. + */ + case 2: + asm volatile("@ __xchg2\n" + "1: ldrexh %0, [%3]\n" + " strexh %1, %2, [%3]\n" + " teq %1, #0\n" + " bne 1b" + : "=&r" (ret), "=&r" (tmp) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; +#endif case 4: asm volatile("@ __xchg4\n" "1: ldrex %0, [%3]\n" -- 1.9.1 ------- Original Message ------- Sender : Will Deacon Date : Oct 05, 2015 18:19 (GMT+05:30) Title : Re: [PATCH v2] arm: Adding support for atomic half word exchange On Mon, Oct 05, 2015 at 03:07:57AM +0000, Sarbojit Ganguly wrote: > This is my second version of the patch which covers the byte exclusive > case as pointed out by you. > Please share your opinion on this. The patch you posted is corrupted (the whitespace looks completely off) so it can't be applied like this. Please take a look at your email/git settings. Will {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I