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From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
To: Robert Marko <robimarko@gmail.com>
Cc: agross@kernel.org, andersson@kernel.org, ansuelsmth@gmail.com,
	conor+dt@kernel.org, devicetree@vger.kernel.org,
	dmitry.baryshkov@linaro.org, ilia.lin@kernel.org,
	konrad.dybcio@linaro.org, krzysztof.kozlowski+dt@linaro.org,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pm@vger.kernel.org, nm@ti.com, rafael@kernel.org,
	robh+dt@kernel.org, sboyd@kernel.org, vireshk@kernel.org
Subject: Re: [PATCH v3 3/3] cpufreq: qcom-nvmem: add support for IPQ8064
Date: Sat, 9 Sep 2023 19:13:23 +0200	[thread overview]
Message-ID: <1923f5dc-9cbe-e2bb-f9a6-5687dfa2faff@wanadoo.fr> (raw)
In-Reply-To: <20230909165739.1036263-3-robimarko@gmail.com>

Le 09/09/2023 à 18:56, Robert Marko a écrit :
> From: Christian Marangi <ansuelsmth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> 
> IPQ8064 comes in 3 families:
> * IPQ8062 up to 1.0GHz
> * IPQ8064/IPQ8066/IPQ8068 up to 1.4GHz
> * IPQ8065/IPQ8069 up to 1.7Ghz
> 
> So, in order to be able to support one OPP table, add support for
> IPQ8064 family based of SMEM SoC ID-s and correctly set the version so
> opp-supported-hw can be correctly used.
> 
> Bit are set with the following logic:
> * IPQ8062 BIT 0
> * IPQ8064/IPQ8066/IPQ8068 BIT 1
> * IPQ8065/IPQ8069 BIT 2
> 
> speed is never fused, only pvs values are fused.
> 
> IPQ806x SoC doesn't have pvs_version so we drop and we use the new
> pattern:
> opp-microvolt-speed0-pvs<PSV_VALUE>
> 
> Example:
> - for ipq8062 psv2
>    opp-microvolt-speed0-pvs2 = < 925000 878750 971250>
> 
> Signed-off-by: Christian Marangi <ansuelsmth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Robert Marko <robimarko-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> Changes in v3:
> * Use enum for SoC version
> * Dont evaluate speed as its not fused, only pvs
> 
> Changes in v2:
> * Include IPQ8064 support
> ---
>   drivers/cpufreq/qcom-cpufreq-nvmem.c | 68 +++++++++++++++++++++++++++-
>   1 file changed, 67 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> index ba9e1d60e5b5..3d93b511db86 100644
> --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> @@ -35,6 +35,12 @@ enum ipq8074_versions {
>   	IPQ8074_ACORN_VERSION,
>   };
>   
> +enum ipq806x_versions {
> +	IPQ8062_VERSION = 0,
> +	IPQ8064_VERSION,
> +	IPQ8065_VERSION,
> +};
> +
>   struct qcom_cpufreq_drv;
>   
>   struct qcom_cpufreq_match_data {
> @@ -208,6 +214,62 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
>   	return ret;
>   }
>   
> +static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev,
> +					     struct nvmem_cell *speedbin_nvmem,
> +					     char **pvs_name,
> +					     struct qcom_cpufreq_drv *drv)
> +{
> +	int speed = 0, pvs = 0, pvs_ver = 0;
> +	int msm_id, ret = 0;
> +	u8 *speedbin;
> +	size_t len;
> +
> +	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
> +
> +	if (IS_ERR(speedbin))
> +		return PTR_ERR(speedbin);
> +
> +	if (len != 4) {
> +		dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
> +		kfree(speedbin);
> +		return -ENODEV;
> +	}
> +
> +	get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver, speedbin);
> +
> +	ret = qcom_smem_get_soc_id(&msm_id);
> +	if (ret)

Missing kfree(speedbin);?

It is freed above and in the normal path, but not here.

(or a new label at the end of the function and a goto. If done this way, 
it can also be used to the test above)

> +		return ret;
> +
> +	switch (msm_id) {
> +	case QCOM_ID_IPQ8062:
> +		drv->versions = BIT(IPQ8062_VERSION);
> +		break;
> +	case QCOM_ID_IPQ8064:
> +	case QCOM_ID_IPQ8066:
> +	case QCOM_ID_IPQ8068:
> +		drv->versions = BIT(IPQ8064_VERSION);
> +		break;
> +	case QCOM_ID_IPQ8065:
> +	case QCOM_ID_IPQ8069:
> +		drv->versions = BIT(IPQ8065_VERSION);
> +		break;
> +	default:
> +		dev_err(cpu_dev,
> +			"SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n",
> +			msm_id);
> +		drv->versions = BIT(IPQ8062_VERSION);
> +		break;
> +	}
> +
> +	/* IPQ8064 speed is never fused. Only pvs values are fused. */
> +	snprintf(*pvs_name, sizeof("speedXX-pvsXX"), "speed%d-pvs%d",
> +		 speed, pvs);
> +
> +	kfree(speedbin);
> +	return ret;
> +}
> +
>   static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
>   					     struct nvmem_cell *speedbin_nvmem,
>   					     char **pvs_name,
> @@ -257,6 +319,10 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = {
>   	.genpd_names = qcs404_genpd_names,
>   };
>   
> +static const struct qcom_cpufreq_match_data match_data_ipq8064 = {
> +	.get_version = qcom_cpufreq_ipq8064_name_version,
> +};
> +
>   static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
>   	.get_version = qcom_cpufreq_ipq8074_name_version,
>   };
> @@ -403,7 +469,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
>   	{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
>   	{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
>   	{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
> -	{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
> +	{ .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
>   	{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
>   	{ .compatible = "qcom,apq8064", .data = &match_data_krait },
>   	{ .compatible = "qcom,msm8974", .data = &match_data_krait },


      reply	other threads:[~2023-09-09 17:13 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-09 16:56 [PATCH v3 1/3] cpufreq: qcom-nvmem: add support for IPQ8074 Robert Marko
2023-09-09 16:56 ` [PATCH v3 2/3] dt-bindings: opp: opp-v2-kryo-cpu: Document named opp-microvolt property Robert Marko
2023-09-12 15:42   ` Rob Herring
2023-09-13 19:34     ` Christian Marangi
2023-09-09 16:56 ` [PATCH v3 3/3] cpufreq: qcom-nvmem: add support for IPQ8064 Robert Marko
2023-09-09 17:13   ` Christophe JAILLET [this message]

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