From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934014AbcHYNAs (ORCPT ); Thu, 25 Aug 2016 09:00:48 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:56937 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932839AbcHYNAq (ORCPT ); Thu, 25 Aug 2016 09:00:46 -0400 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: Kishon Vijay Abraham I , Gabriele Paoloni , David Daney , "linux-pci@vger.kernel.org" , Carlos Palminha , Thierry Reding , Tanmay Inamdar , Joao Pinto , Pratyush Anand , Murali Karicheri , Jason Cooper , Simon Horman , "bhelgaas@google.com" , Mingkai Hu , "linux-omap@vger.kernel.org" , Thomas Petazzoni , Jingoo Han , Richard Zhu , "linux-kernel@vger.kernel.org" , Stanimir Varbanov , Minghuan Lian , Zhou Wang , Ley Foon Tan , Roy Zang , Lucas Stach Subject: Re: Support for configurable PCIe endpoint Date: Thu, 25 Aug 2016 14:59:28 +0200 Message-ID: <1944530.NcryPj8uKU@wuerfel> User-Agent: KMail/5.1.3 (Linux/4.4.0-31-generic; KDE/5.18.0; x86_64; ; ) In-Reply-To: <57B5B4A1.9030308@ti.com> References: <57A18927.9070003@ti.com> <2422602.ltmdGR0pWX@wuerfel> <57B5B4A1.9030308@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:kRZhdyUIyZUfH63ZZE67DZiJlKYLHRXTqGKw7fzXGM+DK9cn/9+ IuCMTKmOPgC8xr+e8g1nhg1gxMfOU8dVya7dFKUdQLfy5jo9hKwlFhYxRsB4vIMKkIQWiBb GbcU2kD0GrtFr7SUVYnA7akGF5bJF3B+HfbplZhlZ3rD+kkBpdtajjr+KEo5qBX/hXPzAbG PnHDYj9GjXIMph5tFfZMA== X-UI-Out-Filterresults: notjunk:1;V01:K0:U6iVU9YIpcs=:RHSpbzQCFRNAKNt4xN0+sm UobwaJM1H9bmwhyO6MuzSPj7kUdDR92UKxUOi4Ic+UMV1HcljlbKXIqoDjmJVSxnzKcPN9eND GZ38rqx+Hnpwdx1i+HxGATvRZzRv/+72nON6dWd/oEKizZ3Hg68yu6lUojgbvvynSUjVVH1Tp FNQZ95/mDNxb8EiPsUh020Y4JtF356rP1SKwKZMCMBGhIAYjZ02/m9DYSsxPLXo09KW2VZ1rr +f2j8FyuZJxZ19FaMJ6xwl83vP7DMoZC0ssfFjCBluZX8bKPkMOuPBLLhXPF21atMTiKUGMR/ IMssKOu4EAqv7W0gW2In1iGJtKajSy8oH56R5YgcrwaFpi6PFovHZVNSFK6pb8k1Zqiqp9emg QmzqNOa2gmWvKtF1HYVlVEPEGQUNeaBDVR5g5sbLTWPnvTXVbnJ8oGvTyctKNRR48ZmXrsR90 +jjDbIEk7LtRkuk9M+szNdiIEBCg3LhjsdrH8UuY5fJqwEbvUEhbkMhROZWmezxem9Fdv/Qfr 8Zs58MN+j1CVBV4R1oDurBm7guIDLvkO8f3gjqZDjekALHLbRtelmatmDL/Q/24wxyfjEnloK PtWIRu9zpo8DTMyTG+LqI1v9EXYBeowIqnDXGPrggrFUlkCPGlyW6qmIeNnqSIsPiQx64myJu ekKDCTccYa5eUF/wgCS7MHVRa6dL0tgOK4Y2Y7WrRuIN4KwV+5bMsU1miYr9MtxC/Vmcz+U7X PhczCTmMmJ8Zrg59 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday, August 18, 2016 6:44:09 PM CEST Kishon Vijay Abraham I wrote: > Hi Arnd, > > On Thursday 04 August 2016 04:43 PM, Arnd Bergmann wrote: > > On Thursday, August 4, 2016 3:32:01 PM CEST Kishon Vijay Abraham I wrote: > >> On Wednesday 03 August 2016 07:09 PM, Joao Pinto wrote: > >>> > >>> You are rising a topic that we are also addressing in Synopsys. > >>> > >>> For the PCIe RC hardware validation we are currently using the standard > >>> pcie-designware and pcie-designware-plat drivers. > >>> > >>> For the Endpoint we have to use an internal software package. Its main purpose > >>> is to initialize the IP registers, eDMA channels and make data transfer to prove > >>> that the everything is working properly. This is done in 2 levels, a custom > >>> driver built and loaded and an application that makes some ioctl to the driver > >>> executing some interesting functions to check the Endpoint status and make some > >>> data exchange. > >> > >> hmm.. the platform I have doesn't have a DMA in PCIe IP > >> (http://www.ti.com/lit/ug/spruhz6g/spruhz6g.pdf). So in your testing does the > >> EP access RC memory? i.e the driver in the RC allocates memory from it's DDR > >> and gives it's DDR address to the EP. The EP then transfers data to this > >> address. (This is a typical use case with ethernet PCIe cards). IIUC that's not > >> simple with configurable EPs. I'd like to know more about your testing though. > > > > > > What's the difference between using the EDMA on that chip or a DMA engine > > that is part of the PCIe bridge? > > Do you mean the difference between using DMA on an EP (like ethernet card or > sata card) and DMA on PCI RC system? or is it the difference between eDMA > within the PCIe IP and system DMA? The latter. You write that there is no DMA in the PCIe IP, but from the perspective of the RC, it should not matter whether the DMA engine is part of the EP logic or behind it. Arnd