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Wed, 30 Oct 2024 08:22:00 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49U8LxjH024621 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Oct 2024 08:21:59 GMT Received: from [10.239.132.41] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 30 Oct 2024 01:21:55 -0700 Message-ID: <197f3520-70a0-4056-b4b4-5325de520ab2@quicinc.com> Date: Wed, 30 Oct 2024 16:21:52 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/4] arm64: dts: qcom: qcs615: add the APPS SMMU node To: Konrad Dybcio , Dmitry Baryshkov CC: , , , , , , , , , , , , References: <20241025030732.29743-1-quic_qqzhou@quicinc.com> <20241025030732.29743-5-quic_qqzhou@quicinc.com> <8a60b729-b312-4afc-835b-a18060ad3f03@oss.qualcomm.com> <8c9804f2-ef4d-412b-97ea-f521dfd35ec2@oss.qualcomm.com> <828c465f-684b-4257-86cb-d9c753fc30f1@oss.qualcomm.com> From: Qingqing Zhou In-Reply-To: <828c465f-684b-4257-86cb-d9c753fc30f1@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: l6jd9oubk9CrZXNtnlo1NWgmNnS3jJrp X-Proofpoint-ORIG-GUID: l6jd9oubk9CrZXNtnlo1NWgmNnS3jJrp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 adultscore=0 mlxscore=0 priorityscore=1501 mlxlogscore=721 impostorscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1011 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410300064 在 10/28/2024 11:46 PM, Konrad Dybcio 写道: > On 26.10.2024 8:18 PM, Dmitry Baryshkov wrote: >> On Fri, Oct 25, 2024 at 06:45:01PM +0200, Konrad Dybcio wrote: >>> On 25.10.2024 1:06 PM, Dmitry Baryshkov wrote: >>>> On Fri, Oct 25, 2024 at 10:54:24AM +0200, Konrad Dybcio wrote: >>>>> On 25.10.2024 5:07 AM, Qingqing Zhou wrote: >>>>>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges >>>>>> to limit DMA address range to 36bit width to align with system >>>>>> architecture. >>>>>> >>>>>> Signed-off-by: Qingqing Zhou >>>>>> --- >>>>> >>>>> You probably also want to mark it `dma-coherent` (see e.g. >>>>> x1e80100.dtsi) >>>> >>>> Is it? I don't think SM6150 had dma-coherent SMMU, at least it wasn't >>>> marked as such. >>> >>> I don't think I have any documentation on this, so.. one way to find out! >> >> I don't have qcs615 at hand, so a purely theoretical question. But how >> should it break if we mark it as dma-coherent, while it is not? > > The board will hang rather quickly > > Konrad Thanks for review comments from Konrad and Dmitry! QCS615 SMMU hardware supports IO-coherency after confirming with Qualcomm hardware team. We also try to add "dma-coherent" for APPS SMMU node and test some SMMU clients, such as UFS and Ethernet, these SMMU clients work well on QCS615. Do you advise and agree to add "dma-coherent" for SMMU node?