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2026 21:56:34.4268 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TP4hGZNo5B2Tfidu6D3Qv8QpxruC9odn4FzwS4ZlKPUYs5pmsXUudho5rBKfHNKXkEkl/qIY4ogfOBIbvwGM2fxWqwozvu4Q8hKxIvYg/Mo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN4PR11MB9965 X-OriginatorOrg: intel.com On 11/4/2026 10:23 AM, Chang S. Bae wrote: > > diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c > index e3660b8b8f38..11c965445bdc 100644 > --- a/arch/x86/kernel/nmi.c > +++ b/arch/x86/kernel/nmi.c > @@ -553,7 +553,7 @@ DEFINE_IDTENTRY_RAW(exc_nmi) > raw_atomic_long_inc(&nsp->idt_calls); > > if (arch_cpu_is_offline(smp_processor_id())) { > - if (microcode_nmi_handler_enabled()) > + if (IS_ENABLED(CONFIG_MICROCODE_LATE_LOADING)) > microcode_offline_nmi_handler(); > return; > } > @@ -715,7 +715,7 @@ DEFINE_FREDENTRY_NMI(exc_nmi) > irqentry_state_t irq_state; > > if (arch_cpu_is_offline(smp_processor_id())) { > - if (microcode_nmi_handler_enabled()) > + if (IS_ENABLED(CONFIG_MICROCODE_LATE_LOADING)) > microcode_offline_nmi_handler(); > return; > } There is a Sashiko comment on this: https://sashiko.dev/#/patchset/20261104182322.578066-1-chang.seok.bae%40intel.com I thought waking up soft-offlined SMT siblings with an NMI was benign. Right now the path is not explicitly gated by the use_nmi flag even though the underlying mechanism is NMI-based. So perhaps it's better to have this reassurance ahead: diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 330c62f6dd32..cf3c02622dc1 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -502,8 +502,11 @@ static void load_primary(unsigned int cpu) unsigned int nr_offl = cpumask_weight(&cpu_offline_mask); bool proceed = true; - /* Kick soft-offlined SMT siblings if required */ - if (!cpu && nr_offl) + /* + * Kick soft-offlined SMT siblings if required. + * Note the mechanism is NMI base. + */ + if (microcode_ops->use_nmi && !cpu && nr_offl) proceed = kick_offline_cpus(nr_offl); /* If the soft-offlined CPUs did not respond, abort */ @@ -511,7 +514,7 @@ static void load_primary(unsigned int cpu) __load_primary(cpu); /* Unconditionally release soft-offlined SMT siblings if required */ - if (!cpu && nr_offl) + if (microcode_ops->use_nmi && !cpu && nr_offl) release_offline_cpus(); } Thanks, Chang