From: Krzysztof Kozlowski <krzk@kernel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Taniya Das <quic_tdas@quicinc.com>,
Jonathan Marek <jonathan@marek.ca>,
Ulf Hansson <ulf.hansson@linaro.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Bryan O'Donoghue <bod@kernel.org>,
Vikash Garodia <vikash.garodia@oss.qualcomm.com>,
Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Stanimir Varbanov <stanimir.varbanov@linaro.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Hans Verkuil <hverkuil@kernel.org>,
Stefan Schmidt <stefan.schmidt@linaro.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Dikshita Agarwal <dikshita@qti.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-media@vger.kernel.org,
Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Subject: Re: [PATCH v3 1/7] dt-bindings: clock: qcom,sm8250-videocc: account for the MX domain
Date: Sun, 8 Feb 2026 10:45:01 +0100 [thread overview]
Message-ID: <19a5b5dd-a3d2-4246-8519-ac9125d8698b@kernel.org> (raw)
In-Reply-To: <mlpe7ph27grv4bulvwlo5lbbsjmwqqfwc3rrfwfcu7tl7qltsu@xrtzonb2t44k>
On 05/02/2026 13:48, Dmitry Baryshkov wrote:
>>
>>> + clock-names:
>>> + items:
>>> + - const: iface
>>> + - const: bi_tcxo
>>> + - const: bi_tcxo_ao
>>> +
>>> + power-domains:
>>> + items:
>>> + - description:
>>> + A phandle and PM domain specifier for the MMCX power domain.
>>> + - description:
>>> + A phandle and PM domain specifier for the MX power domain.
>>
>> This is an ABI break, so please say in the commit what was not working
>> or why this ABI break is really justified. Currently you just give a
>> hint that it is needed for PLL configuration, but honestly - why would
>> we care to configure PLL if everything was working correct before?
>
> I must admit, I c&p'ed the commit message from [1] which was ack'ed by
> Rob and accepted into the kernel. What is the difference?
No difference. To me both are insufficiently explained as fixes, but
other maintainer might have different opinion. I don't mind that.
>
> [1] https://lore.kernel.org/all/20250530-videocc-pll-multi-pd-voting-v5-1-02303b3a582d@quicinc.com/
>
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-02-08 9:45 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-04 0:59 [PATCH v3 0/7] media: qcom: iris/venus: fix power domain handling on SM8250 Dmitry Baryshkov
2026-02-04 0:59 ` [PATCH v3 1/7] dt-bindings: clock: qcom,sm8250-videocc: account for the MX domain Dmitry Baryshkov
2026-02-05 11:31 ` Krzysztof Kozlowski
2026-02-05 12:03 ` Konrad Dybcio
2026-02-05 12:48 ` Dmitry Baryshkov
2026-02-08 9:45 ` Krzysztof Kozlowski [this message]
2026-02-04 0:59 ` [PATCH v3 2/7] media: dt-bindings: qcom,sm8250-venus: sort out power domains Dmitry Baryshkov
2026-02-05 11:32 ` Krzysztof Kozlowski
2026-02-05 12:49 ` Dmitry Baryshkov
2026-02-04 0:59 ` [PATCH v3 3/7] media: iris: scale MMCX power domain on SM8250 Dmitry Baryshkov
2026-02-05 10:39 ` Dikshita Agarwal
2026-02-05 10:55 ` Dmitry Baryshkov
2026-02-04 0:59 ` [PATCH v3 4/7] media: venus: " Dmitry Baryshkov
2026-02-05 6:14 ` Dikshita Agarwal
2026-02-04 0:59 ` [PATCH v3 5/7] arm64: dts: qcom: sm8250: add MX power domain to the video CC Dmitry Baryshkov
2026-02-04 0:59 ` [PATCH v3 6/7] arm64: dts: qcom: sm8250: sort out Iris power domains Dmitry Baryshkov
2026-02-05 6:58 ` Dikshita Agarwal
2026-02-04 0:59 ` [PATCH v3 7/7] arm64: dts: qcom: sm8250: correct frequencies in the Iris OPP table Dmitry Baryshkov
2026-02-05 6:59 ` Dikshita Agarwal
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