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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=VqC2kO2n c=1 sm=1 tr=0 ts=6ace34b8 cx=c_pps a=g1v0Z557R90hA0UpD/5Yag==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=zkeY3IreNFxg1TzoVDwA:9 a=QEXdDO2ut3YA:10 a=MFSWADHSvvjO3QEy5MdX:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: 9a8ogo8SDCUOfgZGFCl3cwZDaD_xddNs X-Proofpoint-ORIG-GUID: 9a8ogo8SDCUOfgZGFCl3cwZDaD_xddNs X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEzMDA1NCBTYWx0ZWRfX89FYDpfxlLvS EXDO82tkddSsl9kl9TOeh/ydU9UDXhuoM4m3cuwDUGMcF4q6unvQAVw+sOlRaCNfaVG4e3Sp3dX FLGbszg0E8OrZ3UzdH4OJkiijS2X1Ds= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEzMDA1NCBTYWx0ZWRfXzRuc4k2ogm2P VSDqO/yE3Ikv2GK78SrBJ0OC4YwY97Ivj83+eU6rcIMzsGDkAqSz4KZ7PYvqdYVJ2ZH2pvA+a+7 rof0eMDq3zXS8K50kzgln9kH82I9ygh3TZUBk0JWU0KRLcr6vDwWnQ/ZqV2IeATYvdciquEE5tC A14VevivDonM6LZ3k/t+j70hbvJ/MlhDkuWKg3pwCX6fvj6ie+Md2IUOP7e3GC8eCOpJOOv7eOr Rrw/st0uBdKKh5pkFarKGxjbmUzYsdIMFRcAbQGULCWsHMKV5HCjr/HmQEID1V7nZ9G+vSWPEVe DxR/rAkhHyLVhgswZLKlO70FF1ISxmHiH03MYvMJOOLBc2uM79w1WOrsMSH0iJitFnnuvQWLl2e M2kY59NiQqgh+Dz2sg+mY6swmotff12pURRgmGHYBdUSjnQuvytnyFVTtWn3B6jASkkICv1j/cK gDyoFJCEJqeBNZkDXNw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 phishscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610130054 On 13-10-2026 12:50 pm, Krzysztof Kozlowski wrote: > On Sat, Oct 10, 2026 at 11:02:42AM +0530, Faisal Hassan wrote: >> On Qualcomm automotive SoC sa8255p, platform resources like clocks, >> interconnects, resets, regulators and GDSC are abstracted and managed >> collectively by firmware. >> >> Add a new binding file for firmware-managed USB controllers where >> access to these resources is exposed as two power domains: >> - Power domain: Controls power supply (GDSC) to the USB controller >> - Bus domain: Controls clocks and interconnects for data transfer >> >> The binding makes power-domains and power-domain-names properties mandatory >> for firmware-managed platforms, while excluding the clocks property since >> clocks are managed through the power domains. >> >> Co-developed-by: Sriram Dash >> Signed-off-by: Sriram Dash >> Signed-off-by: Faisal Hassan >> --- >> .../bindings/usb/qcom,sa8255p-dwc3.yaml | 119 ++++++++++++++++++ >> 1 file changed, 119 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/usb/qcom,sa8255p-dwc3.yaml >> >> diff --git a/Documentation/devicetree/bindings/usb/qcom,sa8255p-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,sa8255p-dwc3.yaml >> new file mode 100644 >> index 000000000000..87f426fdbd70 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/usb/qcom,sa8255p-dwc3.yaml >> @@ -0,0 +1,119 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/usb/qcom,sa8255p-dwc3.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm SA8255P USB3 Controller with Firmware-Managed Resources >> + >> +maintainers: >> + - Wesley Cheng >> + - Faisal Hassan >> + >> +description: >> + USB controller on Qualcomm SA8255P automotive SoC where platform resources >> + such as clocks, interconnects, resets, regulators and the GDSC are >> + abstracted and managed collectively by firmware through SCMI (System >> + Control and Management Interface). >> + >> + Access to these firmware-managed resources is exposed as two power >> + domains, one gating the power supply (GDSC) to the controller, and one >> + gating the clocks and interconnects used for data transfer. >> + >> +properties: >> + compatible: >> + const: qcom,sa8255p-dwc3 >> + >> + reg: >> + maxItems: 1 >> + >> + interrupts: >> + minItems: 5 >> + maxItems: 6 >> + >> + interrupt-names: >> + minItems: 5 >> + items: >> + - const: dwc_usb3 >> + - const: pwr_event >> + - const: hs_phy_irq >> + - const: dp_hs_phy_irq >> + - const: dm_hs_phy_irq >> + - const: ss_phy_irq > > That's still unexpectedly flexible. > Ok, I'll drop minItems so the list is fixed at 6 entries: interrupts: maxItems: 6 interrupt-names: items: - const: dwc_usb3 - const: pwr_event - const: hs_phy_irq - const: dp_hs_phy_irq - const: dm_hs_phy_irq - const: ss_phy_irq >> + >> + power-domains: >> + minItems: 2 > > Drop > >> + maxItems: 2 >> + >> + power-domain-names: >> + items: >> + - const: power >> + - const: bus > > I don't see how did this improve. I asked to use existing bindings as > reference, so why aren't these power and perf? You wrote that bus > controls clocks and interconnect, so is this something different than > perf domain is doing for sa8255? > The sa8255 "perf" domains (e.g. GENI) are SCMI performance-protocol domains with OPP levels. USB "bus" is a plain SCMI power domain with no levels, only on/off, so "perf" would be misleading. I'd like to keep "bus", and will drop the redundant minItems. >> + >> + resets: >> + maxItems: 1 >> + >> + iommus: >> + maxItems: 1 >> + >> + phys: >> + minItems: 1 >> + maxItems: 2 > > phys should be afixed, constrained. > >> + >> + phy-names: >> + minItems: 1 >> + maxItems: 2 > > This as well. > Sure, will modify as below. phys: maxItems: 2 phy-names: items: - const: usb2-phy - const: usb3-phy >> + >> + dma-coherent: true >> + >> + # Firmware-managed platforms do not use direct clock/interconnect control >> + clocks: false >> + clock-names: false >> + interconnects: false >> + interconnect-names: false > > Drop all four above. Not sure why do you need them. > Sure. >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - interrupt-names >> + - power-domains >> + - power-domain-names >> + - resets > > I guess phys and phy-names as well. > Sure, will add both. >> + >> +allOf: >> + - $ref: snps,dwc3-common.yaml# > > Best regards, > Krzysztof Let me know if these changes look OK, and I'll send v4 with them. Thanks, Faisal