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Tue, 10 Nov 2026 12:35:43 -0600 Message-ID: <19e0180b-5d2a-7af7-cb00-d7d640e64f71@amd.com> Date: Tue, 10 Nov 2026 10:35:43 -0800 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH RESEND V1 1/4] accel/amdxdna: Add NPU10 and NPU11 devices Content-Language: en-US To: David Zhang , , , , , , CC: , References: <20261104224302.643329-1-yidong.zhang@amd.com> <20261104224302.643329-2-yidong.zhang@amd.com> From: Lizhi Hou In-Reply-To: <20261104224302.643329-2-yidong.zhang@amd.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW3PEPF00001658:EE_|PH7PR12MB7795:EE_ X-MS-Office365-Filtering-Correlation-Id: bb12b83c-c76e-447c-4bd4-08df3f596e99 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|23010399003|4143699003|10067099003|11063799006|56012099006|261022105027099003|261022075727099003|261009223027099003|261102123227099003|261026140227099003|261028144727099003|261026121527099003|261021121427099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0o+L9LgpMkBMnm+eSe3xFqjsBq0EijMOvXAg8a66sd39YBZp//lwIcbVUP/B1gZuDDfcSjJ05nrH53VVcwm+ooFbLmIR+ZTMb7lqjDdm89A1yg9wydCyDf0JfYzizpgFl3osTYJ7t045j2W0uU414QJQ17/DDvuU566ekH7HwL+2nU+KzGNQBzGJKumBCFGx3pZi/yN5A8aoFAbdW7hiILIgW1HfcOVjOR8XfS2SvYK4/B1jRsmXfy9mLvgnXHC3kO9X464Morz4arAXtqoAP1Fpk0i8yY3poVRIhLD74wNREH7PRS3kLstk+AskDZjVrGp1pfxGKrHV+ZusPoLP3FGU/uLyjexdfGYZ827XXgp1V/zAqEmcRvykFQmmnD+1iXPDe+qrYY5wfod+toj6Z5p66N+zjFqrs4v6EZ19Z5v95b1MMTYq/YVslYu7blXz X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2026 18:35:44.8769 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb12b83c-c76e-447c-4bd4-08df3f596e99 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MW3PEPF00001658.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7795 On 11/4/26 14:42, David Zhang wrote: > NPU3 revisions 0x14 and 0x15 are NPU10 and NPU11. Add their classic, > PF and VF devices with their firmware files and report each by its own > name. They otherwise use the NPU3 settings. > > Signed-off-by: David Zhang > --- > drivers/accel/amdxdna/amdxdna_pci_drv.c | 14 +++++ > drivers/accel/amdxdna/amdxdna_pci_drv.h | 6 ++ > drivers/accel/amdxdna/npu3_regs.c | 78 +++++++++++++++++++++++++ > 3 files changed, 98 insertions(+) > > diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c > index f233eb70a295..685fe1a7dd56 100644 > --- a/drivers/accel/amdxdna/amdxdna_pci_drv.c > +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c > @@ -37,6 +37,14 @@ MODULE_FIRMWARE("amdnpu/17f1_13/npu.sbin"); > MODULE_FIRMWARE("amdnpu/17f1_13/cert.sbin"); > MODULE_FIRMWARE("amdnpu/17f2_13/npu.sbin"); > MODULE_FIRMWARE("amdnpu/17f2_13/cert.sbin"); > +MODULE_FIRMWARE("amdnpu/17f1_14/npu.sbin"); > +MODULE_FIRMWARE("amdnpu/17f1_14/cert.sbin"); > +MODULE_FIRMWARE("amdnpu/17f2_14/npu.sbin"); > +MODULE_FIRMWARE("amdnpu/17f2_14/cert.sbin"); > +MODULE_FIRMWARE("amdnpu/17f1_15/npu.sbin"); > +MODULE_FIRMWARE("amdnpu/17f1_15/cert.sbin"); > +MODULE_FIRMWARE("amdnpu/17f2_15/npu.sbin"); > +MODULE_FIRMWARE("amdnpu/17f2_15/cert.sbin"); > > /* > * 0.0: Initial version > @@ -81,6 +89,12 @@ static const struct amdxdna_device_id amdxdna_ids[] = { > { 0x17f1, 0x13, &dev_npu3_classic_info }, > { 0x17f2, 0x13, &dev_npu3_pf_info }, > { 0x17f3, 0x13, &dev_npu3_vf_info }, > + { 0x17f1, 0x14, &dev_npu10_classic_info }, > + { 0x17f2, 0x14, &dev_npu10_pf_info }, > + { 0x17f3, 0x14, &dev_npu10_vf_info }, > + { 0x17f1, 0x15, &dev_npu11_classic_info }, > + { 0x17f2, 0x15, &dev_npu11_pf_info }, > + { 0x17f3, 0x15, &dev_npu11_vf_info }, > {0} > }; > > diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h > index 27593190dcf6..5ca32c5b1de0 100644 > --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h > +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h > @@ -187,6 +187,12 @@ extern const struct amdxdna_dev_info dev_npu1_info; > extern const struct amdxdna_dev_info dev_npu3_classic_info; > extern const struct amdxdna_dev_info dev_npu3_pf_info; > extern const struct amdxdna_dev_info dev_npu3_vf_info; > +extern const struct amdxdna_dev_info dev_npu10_classic_info; > +extern const struct amdxdna_dev_info dev_npu10_pf_info; > +extern const struct amdxdna_dev_info dev_npu10_vf_info; > +extern const struct amdxdna_dev_info dev_npu11_classic_info; > +extern const struct amdxdna_dev_info dev_npu11_pf_info; > +extern const struct amdxdna_dev_info dev_npu11_vf_info; > extern const struct amdxdna_dev_info dev_npu4_info; > extern const struct amdxdna_dev_info dev_npu5_info; > extern const struct amdxdna_dev_info dev_npu6_info; > diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c > index cff99ddd3a55..4d38aeaea6d0 100644 > --- a/drivers/accel/amdxdna/npu3_regs.c > +++ b/drivers/accel/amdxdna/npu3_regs.c > @@ -197,3 +197,81 @@ const struct amdxdna_dev_info dev_npu3_classic_info = { > .cert_feature_tbl = npu3_cert_feature_table, > .ops = &aie4_classic_ops, > }; > + > +const struct amdxdna_dev_info dev_npu10_pf_info = { > + .mbox_bar = NPU3_MBOX_BAR, > + .sram_bar = NPU3_MBOX_BUFFER_BAR, > + .psp_bar = NPU3_PSP_BAR_INDEX, > + .smu_bar = NPU3_SMU_BAR_INDEX, > + .default_vbnv = "RyzenAI-npu10-pf", > + .device_type = AMDXDNA_DEV_TYPE_PF, > + .dev_priv = &npu3_dev_priv, > + .fw_feature_tbl = npu3_fw_feature_table, > + .cert_feature_tbl = npu3_cert_feature_table, > + .ops = &aie4_pf_ops, > +}; > + > +const struct amdxdna_dev_info dev_npu10_vf_info = { > + .mbox_bar = NPU3_MBOX_BAR, > + .sram_bar = NPU3_MBOX_BUFFER_BAR, > + .doorbell_bar = NPU3_DOORBELL_BAR, > + .default_vbnv = "RyzenAI-npu10-vf", > + .device_type = AMDXDNA_DEV_TYPE_UMQ, > + .dev_priv = &npu3_dev_vf_priv, > + .fw_feature_tbl = npu3_fw_feature_table, > + .cert_feature_tbl = npu3_cert_feature_table, > + .ops = &aie4_vf_ops, > +}; > + > +const struct amdxdna_dev_info dev_npu10_classic_info = { > + .mbox_bar = NPU3_MBOX_BAR, > + .sram_bar = NPU3_MBOX_BUFFER_BAR, > + .psp_bar = NPU3_PSP_BAR_INDEX, > + .smu_bar = NPU3_SMU_BAR_INDEX, > + .doorbell_bar = NPU3_DOORBELL_BAR, > + .default_vbnv = "RyzenAI-npu10", > + .device_type = AMDXDNA_DEV_TYPE_UMQ, > + .dev_priv = &npu3_dev_priv, > + .fw_feature_tbl = npu3_fw_feature_table, > + .cert_feature_tbl = npu3_cert_feature_table, > + .ops = &aie4_classic_ops, > +}; > + > +const struct amdxdna_dev_info dev_npu11_pf_info = { > + .mbox_bar = NPU3_MBOX_BAR, > + .sram_bar = NPU3_MBOX_BUFFER_BAR, > + .psp_bar = NPU3_PSP_BAR_INDEX, > + .smu_bar = NPU3_SMU_BAR_INDEX, > + .default_vbnv = "RyzenAI-npu11-pf", > + .device_type = AMDXDNA_DEV_TYPE_PF, > + .dev_priv = &npu3_dev_priv, > + .fw_feature_tbl = npu3_fw_feature_table, > + .cert_feature_tbl = npu3_cert_feature_table, > + .ops = &aie4_pf_ops, > +}; > + > +const struct amdxdna_dev_info dev_npu11_vf_info = { > + .mbox_bar = NPU3_MBOX_BAR, > + .sram_bar = NPU3_MBOX_BUFFER_BAR, > + .doorbell_bar = NPU3_DOORBELL_BAR, > + .default_vbnv = "RyzenAI-npu11-vf", > + .device_type = AMDXDNA_DEV_TYPE_UMQ, > + .dev_priv = &npu3_dev_vf_priv, > + .fw_feature_tbl = npu3_fw_feature_table, > + .cert_feature_tbl = npu3_cert_feature_table, > + .ops = &aie4_vf_ops, > +}; > + > +const struct amdxdna_dev_info dev_npu11_classic_info = { > + .mbox_bar = NPU3_MBOX_BAR, > + .sram_bar = NPU3_MBOX_BUFFER_BAR, > + .psp_bar = NPU3_PSP_BAR_INDEX, > + .smu_bar = NPU3_SMU_BAR_INDEX, > + .doorbell_bar = NPU3_DOORBELL_BAR, > + .default_vbnv = "RyzenAI-npu11", > + .device_type = AMDXDNA_DEV_TYPE_UMQ, > + .dev_priv = &npu3_dev_priv, > + .fw_feature_tbl = npu3_fw_feature_table, > + .cert_feature_tbl = npu3_cert_feature_table, > + .ops = &aie4_classic_ops, > +}; Reviewed-by: Lizhi Hou