From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752062AbdEDJBQ (ORCPT ); Thu, 4 May 2017 05:01:16 -0400 Received: from authsmtp70.register.it ([195.110.101.54]:41553 "EHLO authsmtp.register.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751567AbdEDJBH (ORCPT ); Thu, 4 May 2017 05:01:07 -0400 X-Greylist: delayed 82329 seconds by postgrey-1.27 at vger.kernel.org; Thu, 04 May 2017 05:01:05 EDT X-Rid: benoit@wsystem.com@90.105.184.123 Subject: Re: [PATCH 1/4] mmc: sdhci-esdhc: Add SDHCI_QUIRK_32BIT_DMA_ADDR To: Arnd Bergmann Cc: Linux Kernel Mailing List , linux-mmc@vger.kernel.org, Ulf Hansson , Adrian Hunter , Fabio Estevam , Wolfram Sang References: <1493805925-3644-1-git-send-email-benoit@wsystem.com> From: =?UTF-8?Q?Beno=c3=aet_Th=c3=a9baudeau?= Organization: Waves System Message-ID: <19f1fd58-6b56-4ba5-4fdf-9cc845b55c27@wsystem.com> Date: Thu, 4 May 2017 11:00:50 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/05/2017 10:47, Arnd Bergmann wrote: > On Wed, May 3, 2017 at 12:05 PM, Benoît Thébaudeau wrote: >> The eSDHC can only DMA from 32-bit-aligned addresses. >> >> This fixes the following test cases of mmc_test: >> 11: Badly aligned write >> 12: Badly aligned read >> 13: Badly aligned multi-block write >> 14: Badly aligned multi-block read >> >> Signed-off-by: Benoît Thébaudeau > > Is this the right description? I thought that SDHCI_QUIRK_32BIT_DMA_ADDR > was for devices that cannot address high memory above 0xffffffff, rather than > requiring a specific alignment. > > If this is indeed an address range problem rather than an alignment problem, > are you sure it is the SD controller that is wrong here, rather than having a > 64-bit DMA capable SDHCI connected to a 32-bit parent bus? In the > latter case, the dma-ranges property in the parent bus should limit > the addressing, not the device. No, this is the right description. This quirk really is about alignment, and not about address range. See: drivers/mmc/host/sdhci.h: >--- /* Controller can only DMA from 32-bit aligned addresses */ #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) <--- drivers/mmc/host/sdhci.c @ sdhci_prepare_data(): >--- offset_mask = 0; [...] if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) offset_mask = 3; [...] if (sg->offset & offset_mask) { DBG("Reverting to PIO because of bad alignment\n"); host->flags &= ~SDHCI_REQ_USE_DMA; break; } <--- Benoît