Re: [PATCH v2 2/3] clk: qcom: dispcc-eliza: Add Eliza display clock controller support

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 3/18/26 11:39 AM, Krzysztof Kozlowski wrote:
> Add a driver for the display clock controller on Qualcomm Eliza SoC,
> which is copied from SM8750 driver plus changes:
> 
> 1. Additional DT_HDMI_PHY_PLL_CLK clock input,
> 2. Eight new HDMI clocks,
> 3. Different PLLs (lucid and pongo).
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---

[...]


> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023-2024, Linaro Ltd.
> + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.

-> Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.

[...]

> +static struct gdsc *disp_cc_eliza_gdscs[] = {
> +	[MDSS_GDSC] = &mdss_gdsc,
> +	[MDSS_INT2_GDSC] = &mdss_int2_gdsc,
> +};
> +
> +static const struct regmap_config disp_cc_eliza_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0xf004, /* 0x10000, 0x10004 and maybe others are for TZ */

0x11014 is the last register

[...]

> +	/* Enable clock gating for MDP clocks */
> +	regmap_update_bits(regmap, DISP_CC_MISC_CMD, BIT(4), BIT(4));

regmap_set_bits()


with that:

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad