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Thu, 03 Apr 2025 00:30:00 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5330TwxS016430 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 3 Apr 2025 00:29:58 GMT Received: from [10.133.33.117] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 2 Apr 2025 17:29:55 -0700 Message-ID: <1a496341-cb74-4636-a3dd-9644dee4fc36@quicinc.com> Date: Thu, 3 Apr 2025 08:29:52 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 9/9] coresight: Consolidate clock enabling To: Leo Yan CC: James Clark , Suzuki K Poulose , Mike Leach , Anshuman Khandual , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , Greg Kroah-Hartman , , , , , Rob Herring References: <20250327113803.1452108-1-leo.yan@arm.com> <20250327113803.1452108-10-leo.yan@arm.com> <8a34b1ac-5681-4cd8-b960-a154d8678fa2@quicinc.com> <20250402090147.GF115840@e132581.arm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <20250402090147.GF115840@e132581.arm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=AMoviu7M c=1 sm=1 tr=0 ts=67edd688 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=ffThkBl6m3zit5QCpSIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: yfsHR0kEGPzQucPIHdfVV8GGndp5T9Xh X-Proofpoint-ORIG-GUID: yfsHR0kEGPzQucPIHdfVV8GGndp5T9Xh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-02_11,2025-04-02_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 impostorscore=0 clxscore=1015 spamscore=0 phishscore=0 mlxlogscore=834 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504020155 On 4/2/2025 5:01 PM, Leo Yan wrote: > Hi Jie, > > [ + Rob ] > > On Wed, Apr 02, 2025 at 08:55:51AM +0800, Jie Gan wrote: > > [...] > >>>>   { >>>> -    struct clk *pclk = NULL; >>>> +    WARN_ON(!pclk); >>>>       if (!dev_is_amba(dev)) { >>>> -        pclk = devm_clk_get_enabled(dev, "apb_pclk"); >>>> -        if (IS_ERR(pclk)) >>>> -            pclk = devm_clk_get_enabled(dev, "apb"); >>>> +        *pclk = devm_clk_get_enabled(dev, "apb_pclk"); >>>> +        if (IS_ERR(*pclk)) >>>> +            *pclk = devm_clk_get_enabled(dev, "apb"); >>>> +        if (IS_ERR(*pclk)) >>>> +            return PTR_ERR(*pclk); >>>> +    } else { >>>> +        /* Don't enable pclk for an AMBA device */ >>>> +        *pclk = NULL; >>> >>> Now the "apb" clock won't be enabled for amba devices. I'm assuming >>> that's fine if the clock was always called "apb_pclk" for them, but the >>> commit that added the new clock name didn't specify any special casing >>> either. >>> >>> Can we have a comment that says it's deliberate? But the more I think >>> about it the more I'm confused why CTCU needed a different clock name to >>> be defined, when all the other Coresight devices use "apb_pclk". >> >> Hi James, >> >> The original clock-name for CTCU is apb_pclk, but the dt-binding maintainer >> request me to change it to apb, that's why the clock name is different from >> others. >> >> I am not why we need apb instead of apb_pclk in dt-binding. Maybe some rules >> have changed for dt-binding requirement. > > My conclusion is that if a device is an Arm Primecell peripheral, it > should use the clock name "apb_pclk" (See the DT binding doc [1]). > > CTCU is not an Arm Primecell peripheral, so it does not need to strictly > follow up the clock naming for Primecell peripheral. > > In Arm CoreSight framework, for code consistency, I would suggest > using the clock naming "apb_pclk" for the APB clock for a newly added > device that even it is not a Primecell peripheral. > > (We don't need to make any change to the CTCU driver, as we need to > remain compatible with existed DTB blobs). > > Cc'ing Rob in case he has any suggestions. Hi Leo, Thanks for the explanation. I agree with you, we should use the "apb_pclk" for the APB clock for a newly added device. Thanks, Jie > > Thanks, > Leo > > [1] Documentation/devicetree/bindings/arm/primecell.yaml