Re: [PATCH 7/9] riscv: dts: ultrarisc: add Rongda M0 board device tree

[Krzysztof Kozlowski <krzk@kernel.org>]

On 15/05/2026 03:18, Jia Wang via B4 Relay wrote:
> From: Jia Wang <wangjia@ultrarisc.com>
> 
> Rongda M0 is an mATX motherboard based on the UltraRISC DP1000 SoC.
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  arch/riscv/boot/dts/Makefile                       |   1 +
>  arch/riscv/boot/dts/ultrarisc/Makefile             |   2 +
>  .../dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi    |  85 ++++++++++++++++
>  arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts | 111 +++++++++++++++++++++
>  4 files changed, 199 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index 69d8751fb17c..702882974251 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -12,3 +12,4 @@ subdir-y += spacemit
>  subdir-y += starfive
>  subdir-y += tenstorrent
>  subdir-y += thead
> +subdir-y += ultrarisc
> diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile
> new file mode 100644
> index 000000000000..d01a770d3cba
> --- /dev/null
> +++ b/arch/riscv/boot/dts/ultrarisc/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-rongda-m0.dtb
> diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi
> new file mode 100644
> index 000000000000..101b416b1079
> --- /dev/null
> +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi
> @@ -0,0 +1,85 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
> + */
> +
> +#include "dp1000.dtsi"
> +
> +&pmx0 {
> +	i2c0_pins: i2c0-pins {
> +		pins = "PA12", "PA13";
> +		function = "func0";
> +		bias-pull-up;
> +		drive-strength = <33>;
> +	};
> +
> +	i2c1_pins: i2c1-pins {
> +		pins = "PB6", "PB7";
> +		function = "func0";
> +		bias-pull-up;
> +		drive-strength = <33>;
> +	};
> +
> +	i2c2_pins: i2c2-pins {
> +		pins = "PC0", "PC1";
> +		function = "func0";
> +		bias-pull-up;
> +		drive-strength = <33>;
> +	};
> +
> +	i2c3_pins: i2c3-pins {
> +		pins = "PC2", "PC3";
> +		function = "func0";
> +		bias-pull-up;
> +		drive-strength = <33>;
> +	};
> +
> +	pciex4a_link_pins: pciex4a-link-pins {
> +		pins = "PC0";
> +		function = "func1";
> +		bias-pull-down;
> +		drive-strength = <33>;
> +	};
> +
> +	pciex4b_link_pins: pciex4b-link-pins {
> +		pins = "PC1";
> +		function = "func1";
> +		bias-pull-down;
> +		drive-strength = <33>;
> +	};
> +
> +	spi0_pins: spi0-pins {
> +		pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7";
> +		function = "func1";
> +		bias-pull-up;
> +		drive-strength = <33>;
> +	};
> +
> +	spi1_pins: spi1-pins {
> +		pins = "PA0", "PA1", "PA2", "PA3";
> +		function = "func0";
> +		bias-pull-up;
> +		drive-strength = <33>;
> +	};
> +
> +	uart0_pins: uart0-pins {
> +		pins = "PA8", "PA9";
> +		function = "func1";
> +		bias-pull-up;
> +		drive-strength = <33>;
> +	};
> +
> +	uart1_pins: uart1-pins {
> +		pins = "PB4", "PB5";
> +		function = "func0";
> +		bias-pull-up;
> +		drive-strength = <33>;
> +	};
> +
> +	uart2_pins: uart2-pins {
> +		pins = "PC4", "PC5";
> +		function = "func0";
> +		bias-pull-up;
> +		drive-strength = <33>;
> +	};
> +};
> diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts
> new file mode 100644
> index 000000000000..6f72d60ad55e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
> + */
> +
> +#include "dp1000-rongda-m0-pinctrl.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	model = "Rongda M0 Board";
> +	compatible = "rongda,m0", "ultrarisc,dp1000";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	gpio-poweroff {
> +		compatible = "gpio-poweroff";
> +		gpios = <&gpio_b 0 GPIO_ACTIVE_HIGH>;
> +		active-delay-ms = <100>;
> +
> +		status = "disabled";

Why is this disabled? You just added final board, so it cannot have any
nodes disabled. Disabled at this point means you add dead code without
explanation.


Best regards,
Krzysztof