From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BB08828399; Tue, 4 Feb 2025 16:45:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738687525; cv=none; b=nTea9ztSaBrgL45YstbaCBMC8D63S8LISWkt2N8PtqflDe+7fKi6PDZgkmbou7Lm2lcm76fladKDe5bGy2hJG0ERvQS51dI3h0R/PRKQ+8G3ETt6JoXAAtfPTYftGjzf0solDaFxaio1GA/1d4F7kRmo8i3vXHYzjZOS6aM8OqY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738687525; c=relaxed/simple; bh=5zUYjqsp1rc0xxpQnCyXSSdQdeKvNFI+5WXBz1zhvzA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=XLQcVqCTNtxI16J6yDOxeQAkbCUK0L83Q5/SnaO80gnMKztl6X2zpJ8Cr4/Xl+TbwfwNC8lH95UTJEwBleh3K0faHvfyzO0KzBPCS6GOI/omlLwF6fgFTQ4ze+O64pg0ppH/6CysPLWsKcI3jZZhqSHyKkGBjcmmX2gNH3TIAsM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: JV7UAgS7Rk2HGLTliDa5lg== X-CSE-MsgGUID: FE4m9sxoSyyoBLRLqiAeAg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 05 Feb 2025 01:45:19 +0900 Received: from [10.24.1.103] (unknown [10.24.1.103]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 3AAD9402E56A; Wed, 5 Feb 2025 01:45:00 +0900 (JST) Message-ID: <1a7b6bf0-5ceb-4308-bb71-6baff945b99d@bp.renesas.com> Date: Tue, 4 Feb 2025 16:44:59 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 07/14] clk: renesas: Add support for R9A09G077 SoC Content-Language: en-GB To: Thierry Bultel , Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> <20250129165122.2980-8-thierry.bultel.yh@bp.renesas.com> From: Paul Barker In-Reply-To: <20250129165122.2980-8-thierry.bultel.yh@bp.renesas.com> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------N4HHktQPozPo0zP20eTBlemk" This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------N4HHktQPozPo0zP20eTBlemk Content-Type: multipart/mixed; boundary="------------GwrN4trEP52IDyjoACCo2w0N"; protected-headers="v1" From: Paul Barker To: Thierry Bultel , Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Message-ID: <1a7b6bf0-5ceb-4308-bb71-6baff945b99d@bp.renesas.com> Subject: Re: [PATCH 07/14] clk: renesas: Add support for R9A09G077 SoC References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> <20250129165122.2980-8-thierry.bultel.yh@bp.renesas.com> In-Reply-To: <20250129165122.2980-8-thierry.bultel.yh@bp.renesas.com> --------------GwrN4trEP52IDyjoACCo2w0N Content-Type: multipart/mixed; boundary="------------tLmamLKW0XDVk1cAJYwNlnb7" --------------tLmamLKW0XDVk1cAJYwNlnb7 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 29/01/2025 16:37, Thierry Bultel wrote: > Add the R9A09G077 SoC specific definitions to the CPG driver. >=20 > Signed-off-by: Thierry Bultel > --- > drivers/clk/renesas/Kconfig | 5 ++ > drivers/clk/renesas/Makefile | 1 + > drivers/clk/renesas/r9a09g077-cpg.c | 100 ++++++++++++++++++++++++++++= > 3 files changed, 106 insertions(+) > create mode 100644 drivers/clk/renesas/r9a09g077-cpg.c >=20 > diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig > index 7ad59be2099d..017ae990d50c 100644 > --- a/drivers/clk/renesas/Kconfig > +++ b/drivers/clk/renesas/Kconfig > @@ -41,6 +41,7 @@ config CLK_RENESAS > select CLK_R9A08G045 if ARCH_R9A08G045 > select CLK_R9A09G011 if ARCH_R9A09G011 > select CLK_R9A09G057 if ARCH_R9A09G057 > + select CLK_R9A09G077 if ARCH_R9A09G077 > select CLK_SH73A0 if ARCH_SH73A0 > =20 > if CLK_RENESAS > @@ -198,6 +199,10 @@ config CLK_R9A09G057 > bool "RZ/V2H(P) clock support" if COMPILE_TEST > select CLK_RZV2H > =20 > +config CLK_R9A09G077 > + bool "RZ/T2H clock support" if COMPILE_TEST > + select CLK_RZT2H > + > config CLK_SH73A0 > bool "SH-Mobile AG5 clock support" if COMPILE_TEST > select CLK_RENESAS_CPG_MSTP > diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefil= e > index bd9f0b54fcda..fe11b10bc451 100644 > --- a/drivers/clk/renesas/Makefile > +++ b/drivers/clk/renesas/Makefile > @@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054) +=3D r9a07g044-cpg.o > obj-$(CONFIG_CLK_R9A08G045) +=3D r9a08g045-cpg.o > obj-$(CONFIG_CLK_R9A09G011) +=3D r9a09g011-cpg.o > obj-$(CONFIG_CLK_R9A09G057) +=3D r9a09g057-cpg.o > +obj-$(CONFIG_CLK_R9A09G077) +=3D r9a09g077-cpg.o > obj-$(CONFIG_CLK_SH73A0) +=3D clk-sh73a0.o > =20 > # Family > diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/= r9a09g077-cpg.c > new file mode 100644 > index 000000000000..0b2895c796d1 > --- /dev/null > +++ b/drivers/clk/renesas/r9a09g077-cpg.c > @@ -0,0 +1,100 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * r9a09g077 Clock Pulse Generator / Module Standby and Software Reset= > + * > + * Copyright (C) 2025 Renesas Electronics Corp. > + * > + */ > + > +#include > +#include > +#include > +#include Please use alphabetical order for these includes. > + > +#include > + > +#include "rzt2h-cpg.h" > + > +enum clk_ids { > + /* Core Clock Outputs exported to DT */ > + /* External Input Clocks */ > + LAST_DT_CORE_CLK =3D R9A09G077_LCDC_CLKD, > + CLK_EXTAL, > + CLK_LOCO, I think the above lines have got slightly mixed up, it should be: /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK =3D R9A09G077_LCDC_CLKD, /* External Input Clocks */ CLK_EXTAL, CLK_LOCO, With these minor changes, Reviewed-by: Paul Barker --=20 Paul Barker --------------tLmamLKW0XDVk1cAJYwNlnb7 Content-Type: application/pgp-keys; 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