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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498ae57a84sm169205e87.62.2025.03.06.04.45.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Mar 2025 04:45:54 -0800 (PST) Message-ID: <1aa77e2e-6bb0-425c-9b5a-64092f8df9a5@oss.qualcomm.com> Date: Thu, 6 Mar 2025 13:45:50 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/8] clk: qcom: common: Manage rpm, configure PLLs & AON clks in really probe To: Jagadeesh Kona , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Taniya Das , Satya Priya Kakitapalli , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250306-videocc-pll-multi-pd-voting-v2-0-0cd00612bc0e@quicinc.com> <20250306-videocc-pll-multi-pd-voting-v2-3-0cd00612bc0e@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250306-videocc-pll-multi-pd-voting-v2-3-0cd00612bc0e@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=HZbuTjE8 c=1 sm=1 tr=0 ts=67c99904 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=yHIa6xKSslqa2ziMgBoA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: O0jPKhYNcy7g23we4NIk8OVdIOJjL7BJ X-Proofpoint-ORIG-GUID: O0jPKhYNcy7g23we4NIk8OVdIOJjL7BJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-06_05,2025-03-06_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 mlxscore=0 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503060096 On 6.03.2025 9:55 AM, Jagadeesh Kona wrote: > Add support for runtime power management, PLL configuration and enabling > critical clocks in qcom_cc_really_probe() to commonize the clock > controller probe. > > The runtime power management is not required for all clock controllers, > hence handle the rpm based on use_rpm flag in clock controller descriptor. > Also the power domains need to be kept enabled during pll configuration, > hence attach all required power domains prior to calling get_sync() on the > device. > > Signed-off-by: Jagadeesh Kona > --- [...] > + * struct qcom_clk_cfg - To maintain list of clocks that needs to be > + * kept ON or misc clock register settings I have some reservations about this name, particularly since 'clk_cfg' has already been used in the msmbus/interconnect space.. Perhaps qcom_clk_reg_settings? > + * @offset: address offset for clock register > + * @mask: bit mask to indicate the bits to update > + */ > +struct qcom_clk_cfg { > + unsigned int offset; > + unsigned int mask; "u32" also, to expand it, we probably want "field" and "val" to replace the calls to regmap_update_bits in some drivers I think we may keep this /\ struct for things like: /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); while keeping a separate u32 array of branch clocks to call qcom_branch_set_clk_en() on - we would then use 3x less memory > +}; > + > struct qcom_cc_desc { > const struct regmap_config *config; > struct clk_regmap **clks; > @@ -39,6 +50,11 @@ struct qcom_cc_desc { > const struct qcom_icc_hws_data *icc_hws; > size_t num_icc_hws; > unsigned int icc_first_node_id; > + struct qcom_clk_cfg *clks_cfg; > + size_t num_clks_cfg; > + struct clk_alpha_pll **plls; Some ancient or "non-standard" SoCs have non-alpha PLLs, please rename this to something like alpha_plls Konrad