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Wed, 05 Feb 2025 05:42:04 -0800 (PST) Message-ID: <1ac208a7-ec63-42fe-b496-5a2e7fd615f2@linaro.org> Date: Wed, 5 Feb 2025 14:42:03 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver To: Dmitry Baryshkov Cc: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250203-drm-msm-phy-pll-cfg-reg-v2-0-862b136c5d22@linaro.org> <20250203-drm-msm-phy-pll-cfg-reg-v2-2-862b136c5d22@linaro.org> <12275e11-eadc-48be-b8c3-9463cdf92698@linaro.org> <2e96ae62-3114-4c7b-bea7-27f6e2009634@linaro.org> <6cba59b9-4852-4cad-95eb-dfecb2e44dc4@linaro.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 05/02/2025 12:23, Dmitry Baryshkov wrote: >>>>>>>> + >>>>>>>> +static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) >>>>>>>> +{ >>>>>>>> + dsi_pll_cmn_clk_cfg1_update(pll, BIT(5), 0); >>>>>>>> } >>>>>>>> >>>>>>>> static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll) >>>>>>>> { >>>>>>>> - u32 data; >>>>>>>> + u32 cfg_1 = BIT(5) | BIT(4); >>>>>>> >>>>>>> Please define these two bits too. >>>>>> >>>>>> Why? They were not defined before. This only moving existing code. >>>>> >>>>> Previously it was just a bit magic. Currently you are adding them as >>>> >>>> No, previous code: >>>> >>>> writel(data | BIT(5) | BIT(4), pll->phy->base + >>>> REG_DSI_7nm_PHY_CMN_CLK_CFG1); >>>> >>>> This is a mask and update in the same time, because: >>>> (data & (BIT(5) | BIT(4)) | BIT(5) | BIT(4) >>>> is just redudant. >>>> >>>> I did not do any logical change, I did not add any mask or field. >>>> Everything was already there. >>> >>> Yes... and no. Previously it was just writel(foo | BIT(5) | BIT(4)). Now >> >> You did not address my comment. Previous code was: >> >> (foo & (BIT(5) | BIT(4)) | BIT(5) | BIT(4) >> >> Just for shorter syntax it was written different way: >> >> foo | BIT(5) | BIT(4) > > Previously it was a simple writel() with some bit magic. Now you call The mask was already there, just implied. > dsi_pll_cmn_clk_cfg1_update() passing the register bit field through > the 'mask' argument. I'm asking to get those masks defined. Is it > possible? Just like before, because implied mask is being removed due to code redundancy. I repeat it for third time already. > > Yes, the code is equivalent and results in the same values being > written to the same registers. > At the same time you have added a logical entity, a masked write. I > want to be able to understand if bits 4 and 5 are a part of the same > register field or they belong to two different fields and can be I know you want to understand it and this is achieved in separate patch, because understanding this is not related to this commit. > written separately. I really don't understand why are we spending so > much time arguing about a simple #define. Okay, in case of drm/msm it > is not a #define, it is . The net result is the > same. I also don't get why simple fix could not be just applied and it has to become some sort of big refactoring. Best regards, Krzysztof