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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7af827f0552sm1965612b3a.51.2025.11.06.01.00.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Nov 2025 01:01:00 -0800 (PST) Message-ID: <1ad1fc7d-7b6e-403e-936c-4c5a12d4e6f4@oss.qualcomm.com> Date: Thu, 6 Nov 2025 17:00:51 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v14 0/5] pci: qcom: Add QCS8300 PCIe support To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Ziyue Zhang References: <20251024095609.48096-1-ziyue.zhang@oss.qualcomm.com> Content-Language: en-US From: Ziyue Zhang In-Reply-To: <20251024095609.48096-1-ziyue.zhang@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=R5UO2NRX c=1 sm=1 tr=0 ts=690c63cf cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=QyXUC8HyAAAA:8 a=IHEL40AIkIxnPEiLsFYA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 2XBpm-sCvOxutJaMwYbkDjIG_65A6RfY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA2MDA3MiBTYWx0ZWRfX86rW6g7isgnI n64IoJWRiKSgURS14vgKqts7I/Dt3+sjh0O796ZFkZ6yzvEXVWNRr/ug8GfKlwoDcCDdohzp5JB 66ijDMYEBhLcwhxmzbWrdIQvAX3B9vHfsJ4qCeNsgmVV9QtO4U0r4WlfxWtuL+qVtLNUDGp4R6G KpAr9qGiucoyVZUxb6vtnkr0Sfbu5QLCkl6ZYqS6ZpsFYL3VHS0RaswSeEZD71wqZ0KDQnI7B8c tht2VA8O1Ri3CBRbG/BY9sor/ye+qKYESd8UKQ/ybDfPbnvdo8I91TlU2qVIDiOIQ7FdWKAePkm 9YJ45KY7G6J78CrQ7YeINTzXvvgqgI/pyjuXYMGRUeOtSCnLWPCyr9orincqDM3OVwbEAMcCFDe tCplVMWGQRW5RFRm6YwFthWugFdwsw== X-Proofpoint-GUID: 2XBpm-sCvOxutJaMwYbkDjIG_65A6RfY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-06_01,2025-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 phishscore=0 adultscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511060072 On 10/24/2025 5:56 PM, Ziyue Zhang wrote: > This series depend on this patch > https://lore.kernel.org/all/20250826-pakala-v2-3-74f1f60676c6@oss.qualcomm.com/ > > This series adds document, phy, configs support for PCIe in QCS8300. > It also adds 'link_down' reset for sa8775p. > > Have follwing changes: > - Add dedicated schema for the PCIe controllers found on QCS8300. > - Add compatible for qcs8300 platform. > - Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. > - Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence. > > Signed-off-by: Krishna chaitanya chundru > Signed-off-by: Ziyue Zhang > --- > Changes in v14: > - rebase patches > - Link to v13: https://lore.kernel.org/all/20250908073848.3045957-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v13: > - Fix dtb error > - Link to v12: https://lore.kernel.org/all/20250905071448.2034594-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v12: > - rebased pcie phy bindings > - Link to v11: https://lore.kernel.org/all/20250826091205.3625138-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v11: > - move phy/perst/wake to pcie bridge node (Mani) > - Link to v10: https://lore.kernel.org/all/20250811071131.982983-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v10: > - Update PHY max_items (Johan) > - Link to v9: https://lore.kernel.org/all/20250725104037.4054070-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v9: > - Fix DTB error (Vinod) > - Link to v8: https://lore.kernel.org/all/20250714081529.3847385-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v8: > - rebase sc8280xp-qmp-pcie-phy change to solve conflicts. > - Add Fixes tag to phy change (Johan) > - Link to v7: https://lore.kernel.org/all/20250625092539.762075-1-quic_ziyuzhan@quicinc.com/ > > Changes in v7: > - rebase qcs8300-ride.dtsi change to solve conflicts. > - Link to v6: https://lore.kernel.org/all/20250529035635.4162149-1-quic_ziyuzhan@quicinc.com/ > > Changes in v6: > - move the qcs8300 and sa8775p phy compatibility entry into the list of PHYs that require six clocks > - Update QCS8300 and sa8775p phy dt, remove aux clock. > - Fixed compile error found by kernel test robot > - Link to v5: https://lore.kernel.org/all/20250507031019.4080541-1-quic_ziyuzhan@quicinc.com/ > > Changes in v5: > - Add QCOM PCIe controller version in commit msg (Mani) > - Modify platform dts change subject (Dmitry) > - Fixed compile error found by kernel test robot > - Link to v4: https://lore.kernel.org/linux-phy/20241220055239.2744024-1-quic_ziyuzhan@quicinc.com/ > > Changes in v4: > - Add received tag > - Fixed compile error found by kernel test robot > - Link to v3: https://lore.kernel.org/lkml/202412211301.bQO6vXpo-lkp@intel.com/T/#mdd63e5be39acbf879218aef91c87b12d4540e0f7 > > Changes in v3: > - Add received tag(Rob & Dmitry) > - Update pcie_phy in gcc node to soc dtsi(Dmitry & Konrad) > - remove pcieprot0 node(Konrad & Mani) > - Fix format comments(Konrad) > - Update base-commit to tag: next-20241213(Bjorn) > - Corrected of_device_id.data from 1.9.0 to 1.34.0. > - Link to v2: https://lore.kernel.org/all/20241128081056.1361739-1-quic_ziyuzhan@quicinc.com/ > > Changes in v2: > - Fix some format comments and match the style in x1e80100(Konrad) > - Add global interrupt for PCIe0 and PCIe1(Konrad) > - split the soc dtsi and the platform dts into two changes(Konrad) > - Link to v1: https://lore.kernel.org/all/20241114095409.2682558-1-quic_ziyuzhan@quicinc.com/ > > > Ziyue Zhang (5): > dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings > for qcs8300 > arm64: dts: qcom: qcs8300: enable pcie0 > arm64: dts: qcom: qcs8300-ride: enable pcie0 interface > arm64: dts: qcom: qcs8300: enable pcie1 > arm64: dts: qcom: qcs8300-ride: enable pcie1 interface > > .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 17 +- > arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 84 +++++ > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 310 +++++++++++++++++- > 3 files changed, 394 insertions(+), 17 deletions(-) > > > base-commit: 72fb0170ef1f45addf726319c52a0562b6913707 Hi Maintainers, It seems the patches get reviewed tag for a long time, can you give this series further comment or help me to merge them ? Thanks very much. BRs Ziyue