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Thu, 6 Aug 2026 11:28:23 -0400 (EDT) Content-Type: multipart/mixed; boundary="------------aPZ88F0pvkjouaGYy7fre0E7" Message-ID: <1ade6c35-7f8a-406d-9c89-8d10218258c6@polyxeno.com> Date: Fri, 7 Aug 2026 01:28:20 +1000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH bpf-next v4 RESEND] m68k, bpf: Add initial BPF JIT compiler support To: Kuan-Wei Chiu , geert@linux-m68k.org, ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com Cc: martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, jserv@ccns.ncku.edu.tw, eleanor15x@gmail.com, marscheng@google.com, linux-kernel@vger.kernel.org, linux-m68k@lists.linux-m68k.org, bpf@vger.kernel.org, Daniel Palmer References: <20260729002737.1008358-1-visitorckw@gmail.com> Content-Language: en-US From: Greg Ungerer In-Reply-To: <20260729002737.1008358-1-visitorckw@gmail.com> This is a multi-part message in MIME format. --------------aPZ88F0pvkjouaGYy7fre0E7 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Kuan-Wei, On 29/7/26 10:27, Kuan-Wei Chiu wrote: > Add a BPF JIT compiler for the m68k architecture. > > The JIT generates m68k machine code targeting m68020+ processors. It > currently excludes 68000/68010 and coldfire processors, as it relies on > 32 bit branch displacements (b.l) to handle large bpf programs. I was interested to see how difficult this would be to get working on a ColdFire target. There is a little more to it than just the 32bit branch displacements. If you limit the target space to ColdFire parts that have an MMU (so parts that have the ISA_B or ISA_C instruction set) then 32bit branch displacements are supported. So that is no longer a problem. The following are issues I hit: 1. lack of movem with pre-decrement and post-increment modes used in quite a few places 2. lack of register exchange instruction ("exg") used in emit_atomic() used in emit_call() used in 64bit bpf shitf operations in emit_alu64_shift() 3. lack of rotate instructions ("ror" and "rox") used for bpf shift operations in emit_alu64_shift() used for endian transformation in emit_bpf_end() Issue (1) is easy to work around, manually manipulating %sp as required with an extra instruction. Issue (2) also is easy enough, needing temporary storage. Issue (3) is annoying and means a bunch more instructions to carry out the equivalent operations. None the less it is not too difficult to modify for. ISA_C does have a "byterev" instruction that would make this really easy - but only the very most modern ColdFire silicon use that (like the 5441x family). The attached patch is my first pass at it. It works and passes the test_bpf.ko module with no failures(*). Surely could be optimized a little more, but good enough to get it working. Tested and running on an M5475 ColdFire target. test_bpf: Summary: 1061 PASSED, 0 FAILED, [1049/1049 JIT'ed] test_bpf: test_tail_calls: Summary: 10 PASSED, 0 FAILED, [10/10 JIT'ed] (*) I did come across a cache flush issue specific to ColdFire - but it is not related to this code and can be worked around. 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