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Fri, 16 Oct 2026 04:08:50 -0700 (PDT) X-Received: by 2002:a05:7022:297:20b0:14a:8df8:56b1 with SMTP id a92af1059eb24-16a5ef28a5bmr27085829c88.22.1792148929254; Fri, 16 Oct 2026 04:08:49 -0700 (PDT) Received: from [10.218.42.145] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1831c4d4675sm5101862c88.21.2026.10.16.04.08.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Oct 2026 04:08:48 -0700 (PDT) Message-ID: <1ae8d4f0-1c32-4dbd-a18e-7a2ce2627efc@oss.qualcomm.com> Date: Fri, 16 Oct 2026 16:38:44 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] PCI: qcom: Advertise hotplug with no command completion support To: Neil Armstrong , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260314-hotplug-v1-1-96ac87d93867@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: n6edfJpL2HWfwCeXStuGoTB5yZtfAp4f X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE2MDA0NCBTYWx0ZWRfX0/CzIyEKHPVJ S+Ua807Zt80ZWV1jP+3LSiM5ogKkNcwQZ8gOtzx5Cg6kWJSIvFWlSf7Wnw0M84V0ZXIZ8AHGKcb XE88AhmjN/c167W2Z9wQBPUMR8RSKbg= X-Authority-Analysis: v=2.4 cv=SrAFe/O0 c=1 sm=1 tr=0 ts=6ad205c4 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=bC-a23v3AAAA:8 a=EUspDBNiAAAA:8 a=ShDbLQTyCWfcQnIfrFwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 a=FO4_E8m0qiDe52t0p3_H:22 X-Proofpoint-ORIG-GUID: n6edfJpL2HWfwCeXStuGoTB5yZtfAp4f X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE2MDA0NCBTYWx0ZWRfX2h9lRQ2F98mH NITEQ7BQ12aZpI55RvwCs/N7OkJnTOBcAJFpnvll6itklEj4Ty4kOKPdYDbA0xY5lcTZe019y9j 2orjDyc/Rj4BJBRHY1YtPfIKZChBhTXLxO3APTwUSPNKVXwat0u5GKpgkGvk7VO6BCkXAAslDmh /0qZWqPydbaf8Un2gDsOEohoBYblaJM+qrmcPkfof0k9A3T3iomkxB+usCbE4eiLjjJ60VbdUy3 3g8gd9+CUNjg3R7y2kZz31dmzT/SclnGgDYxpWEvyB28DsBTyLNEVRa/d91Y8B5/FLx1xCQIhlV lDAxq4qeLAKX/O0P4bF2/J6Ll0klkX2DFCzC+ERzZqpNLcawuI3k4WYjSvbDgJA/yYKPsyaUh73 PB5EQObwLPS2mPp4hge3YEMrGjxOaGM+gAnr8XABTE0z36uQy3CdwUkKdber8o+5xV8d4pD5dq7 vQwFkFd2D0o2XACTe9A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-16_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 bulkscore=0 spamscore=0 phishscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610160044 On 10/16/2026 3:54 PM, Neil Armstrong wrote: > Hi, > > On 3/14/26 02:56, Krishna Chaitanya Chundru wrote: >> QCOM PCIe controller advertise hotplug capability in hardware but do not >> support hotplug command completion. As a result, the PCI core registers >> the pciehp service and issues hotplug commands that never gets completions, >> leading to repeated timeout warnings and multi-second delays during boot >> and suspend/resume. >> >> Commit a54db86ddc153 ("PCI: qcom: Do not advertise hotplug capability for >> IPs v2.7.0 and v1.9.0") avoided these timeouts by clearing the Hot-Plug >> Capability bit entirely, which also disabled all hotplug functionality. >> >> Instead of disabling hotplug, mark these controllers as not supporting >> command completion by setting the No Command Completed Support (NCCS) bit >> in the Slot Capabilities register. This prevents the PCI hotplug driver >> from waiting for commands completion while still allowing hotplug-related >> functionality such as Data Link Layer state change events. > > I'm a little late to the party, but marking the RC as Hotplus means the bridge > is marked as is_pciehp and pci_bridge_d3_possible() returns false. > > This means this breaks D3Cold support completely since in > __pci_host_common_d3cold_possible() > we now check all PCI devices, including bridges, and the RC is not set in > D3Hot anymore. > > The only way to enable D3Cold is to pass pcie_port_pm=force to allow D3 on all > Hotplug bridges. Which may be wrong on TB bridges. > Hi Neil, can you enable hotplug driver and use this patch [1], that should solve the issue. [1] https://patch.msgid.link/20260729165005.896725-1-manivannan.sadhasivam@oss.qualcomm.com > Neil > >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >>   drivers/pci/controller/dwc/pcie-qcom.c | 2 +- >>   1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c >> b/drivers/pci/controller/dwc/pcie-qcom.c >> index >> 67a16af69ddc75fca1b123e70715e692a91a9135..a2924610f3625f2456a491473c135840e31bafb9 >> 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -358,7 +358,7 @@ static void qcom_pcie_clear_hpc(struct dw_pcie *pci) >>       dw_pcie_dbi_ro_wr_en(pci); >>         val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); >> -    val &= ~PCI_EXP_SLTCAP_HPC; >> +    val |= PCI_EXP_SLTCAP_NCCS; >>       writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); >>         dw_pcie_dbi_ro_wr_dis(pci); >> >> --- >> base-commit: 0257f64bdac7fdca30fa3cae0df8b9ecbec7733a >> change-id: 20260313-hotplug-4c296595b5b8 >> >> Best regards, >