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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id u20-20020a05600c211400b0040642a1df1csm15081271wml.25.2023.10.10.12.52.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Oct 2023 12:52:53 -0700 (PDT) Message-ID: <1aea4a86-7f7c-46ee-9cbe-655eb7663c2a@linaro.org> Date: Tue, 10 Oct 2023 21:52:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 4/4] ARM: dts: qcom: ipq8064: Add CPU OPP table Content-Language: en-US To: Christian Marangi Cc: Robert Marko , ilia.lin@kernel.org, vireshk@kernel.org, nm@ti.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, rafael@kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20230930102218.229613-1-robimarko@gmail.com> <20230930102218.229613-4-robimarko@gmail.com> <65255c81.050a0220.141f8.7b8f@mx.google.com> From: Konrad Dybcio In-Reply-To: <65255c81.050a0220.141f8.7b8f@mx.google.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/10/23 16:15, Christian Marangi wrote: > On Tue, Oct 10, 2023 at 03:40:32PM +0200, Konrad Dybcio wrote: >> >> >> On 9/30/23 12:21, Robert Marko wrote: >>> From: Christian Marangi >>> >>> Add CPU OPP table for IPQ8062, IPQ8064 and IPQ8065 SoC. >>> Use opp-supported-hw binding to correctly enable and disable the >>> frequency as IPQ8062 supports up to 1.0Ghz, IPQ8064 supports up to >>> 1.4GHz with 1.2GHz as an additional frequency and IPQ8065 supports >>> 1.7GHZ but doesn't have 1.2GHZ frequency and has to be disabled. >>> >>> Signed-off-by: Christian Marangi >>> Signed-off-by: Robert Marko >>> --- >> Christian/Robert, can you provide a downstream source for this? >> > > Sure, consider that everything is with +/-5%. Hm, so you're e.g. putting ipq8062 384MHz voltage for PVS3 equal to 0.95*800000 = 760000, but I'm not sure if it's a good idea? The comment in downstream: "These are based on +/-5% Margin on the VDD_APCx that is advertised in our Datasheet across Temperature" suggests this is already not very accurate, and betting that the lower threshold works on all chips is probably not the best idea. Konrad