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bh=/LeaUuNIif0a7QqXvpOSXqDJD3RK/W+5O3RV2jm8k54=; b=Di/6V2jbzjqycIhHYF+DH/4oT+qbTxPSGhwo60Ck7cyYMHDxiFPBe7S4Mi3mdt7je6/DI1nVOFSpUoMb8iCptBL0HScm/EO4TbhwmL5o6i5YpNnTvrD2k1xIAM9KcdjmaJN+BtarVo1+S49E8fZGuRqUn1yrOuYPivKBKQ+aCmA= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=wolfvision.net; Received: from DU0PR08MB9155.eurprd08.prod.outlook.com (2603:10a6:10:416::5) by PA4PR08MB6079.eurprd08.prod.outlook.com (2603:10a6:102:ee::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5880.8; Mon, 28 Nov 2022 06:52:42 +0000 Received: from DU0PR08MB9155.eurprd08.prod.outlook.com ([fe80::3643:6226:28c:e637]) by DU0PR08MB9155.eurprd08.prod.outlook.com ([fe80::3643:6226:28c:e637%2]) with mapi id 15.20.5880.008; Mon, 28 Nov 2022 06:52:42 +0000 Message-ID: <1afb1586-ebd9-6b99-580b-531e8ba7df32@wolfvision.net> Date: Mon, 28 Nov 2022 07:52:39 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: Re: [PATCHv4 6/7] arm64: dts: rockchip: Add rock-5a board Content-Language: en-US To: Sebastian Reichel , Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Linus Walleij , Christopher Obbard , Benjamin Gaignard , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@collabora.com References: <20221124144928.35381-1-sebastian.reichel@collabora.com> <20221124144928.35381-7-sebastian.reichel@collabora.com> From: Michael Riesch In-Reply-To: <20221124144928.35381-7-sebastian.reichel@collabora.com> Content-Type: text/plain; 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While the hardware > offers plenty of peripherals and connectivity this basic implementation > just handles things required to access eMMC, UART and Ethernet (i.e. > enough to successfully boot Linux). > > Tested-by: Benjamin Gaignard > Signed-off-by: Sebastian Reichel Isn't your Signed-off-by: tag supposed to come first? (This question also holds for patches 1, 2 (your S-o-B before the Reviewed-by) and 4 of this series. > --- > arch/arm64/boot/dts/rockchip/Makefile | 1 + > .../boot/dts/rockchip/rk3588s-rock-5a.dts | 63 +++++++++++++++++++ > 2 files changed, 64 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile > index 12ed53de11eb..31fa55750a0f 100644 > --- a/arch/arm64/boot/dts/rockchip/Makefile > +++ b/arch/arm64/boot/dts/rockchip/Makefile > @@ -73,3 +73,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb > diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts > new file mode 100644 > index 000000000000..b9d1ade62b4c > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts > @@ -0,0 +1,63 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > + > +/dts-v1/; > + > +#include > +#include > +#include "rk3588s.dtsi" > + > +/ { > + model = "Radxa Rock 5A Board"; > + compatible = "radxa,rock-5a", "rockchip,rk3588s"; > + > + aliases { > + mmc1 = &sdhci; > + serial2 = &uart2; > + }; > + > + chosen { > + stdout-path = "serial2:1500000n8"; > + }; > +}; > + > +&gmac1 { > + clock_in_out = "output"; > + phy-handle = <&rgmii_phy1>; > + phy-mode = "rgmii-rxid"; > + pinctrl-0 = <&gmac1_miim > + &gmac1_tx_bus2 > + &gmac1_rx_bus2 > + &gmac1_rgmii_clk > + &gmac1_rgmii_bus>; > + pinctrl-names = "default"; > + rx_delay = <0x3e>; Documentation says that the MAC should not add an RX delay in the "rgmii-rxid" case, but it is specified. Is this really necessary? > + tx_delay = <0x3a>; > + status = "okay"; > +}; > + > +&mdio1 { > + rgmii_phy1: ethernet-phy@1 { > + /* RTL8211F */ > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0x1>; > + reset-assert-us = <20000>; > + reset-deassert-us = <100000>; > + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; No pinctrl required for this reset pin? With this addressed: Reviewed-by: Michael Riesch Thanks and best regards, Michael > + }; > +}; > + > +&sdhci { > + bus-width = <8>; > + no-sdio; > + no-sd; > + non-removable; > + max-frequency = <200000000>; > + mmc-hs400-1_8v; > + mmc-hs400-enhanced-strobe; > + status = "okay"; > +}; > + > +&uart2 { > + pinctrl-0 = <&uart2m0_xfer>; > + status = "okay"; > +};