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Wed, 18 Mar 2026 00:21:28 -0700 (PDT) X-Received: by 2002:a17:902:e94d:b0:2b0:608d:d8a8 with SMTP id d9443c01a7336-2b06e3230femr23641015ad.1.1773818487824; Wed, 18 Mar 2026 00:21:27 -0700 (PDT) Received: from [10.217.223.121] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b06e619ec3sm17610455ad.69.2026.03.18.00.21.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Mar 2026 00:21:27 -0700 (PDT) Message-ID: <1b1028b3-22c9-4b00-952f-804f192d8870@oss.qualcomm.com> Date: Wed, 18 Mar 2026 12:51:18 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 01/12] dt-bindings: crypto: qcom,ice: Allow power-domain and iface clk To: Dmitry Baryshkov Cc: Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Manivannan Sadhasivam , cros-qcom-dts-watchers@chromium.org, Eric Biggers , Jingyi Wang , Tengfei Fan , Bartosz Golaszewski , David Wronek , Luca Weiss , Neil Armstrong , Melody Olvera , Alexander Koskovich , Brian Masney , Neeraj Soni , Gaurav Kashyap , linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Kuldeep Singh References: <20260317-qcom_ice_power_and_clk_vote-v3-0-53371dbabd6a@oss.qualcomm.com> <20260317-qcom_ice_power_and_clk_vote-v3-1-53371dbabd6a@oss.qualcomm.com> Content-Language: en-US From: Harshal Dev In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=A7Zh/qWG c=1 sm=1 tr=0 ts=69ba5279 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=vZp64IP-UYAUPCcu32UA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: WzxU3wqAysqzao37GQF6H3u8dLgSy9Sh X-Proofpoint-ORIG-GUID: WzxU3wqAysqzao37GQF6H3u8dLgSy9Sh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE4MDA2MSBTYWx0ZWRfXyh8Ilf4pfdoZ 0g9NbZ7hwM/fEh12i3hfHVasJVgdfjkZ9QFedb8TTnPk4mtVyngIgGqxTeubGPfH7zAfxvrkSZD fy6uyu2WbaL510gCGMowb1Xz4hpGZYC/22ubHjTn3Rzum398tLPLHzBJHIPUvJSz/FmqTLf9gN4 BY+MXBDGqoWI+vsI8KikrPZAAXXsqdf32Mh3eX8WKl8xtuWyew2TLxOgIq9CIQJvxRn1ygwV2bb skJsCCt3K3R0ZgFPoxHKzOTpuxF437Ob7r7I5dQnIa27FVEhKx49jp1+2SXyq16yO39OpEJueGL QWlEVspgdexHAZhcvLhHKLJiHyp93gIBAJXpwRFfbhGV4FUSDM/lGcyXtGJK17Wu3HnlfoRgyvn /gvoGV71aDcDrTDrAa4K4KhSmZrYXzCMHleI1G8T63X3du2GJyRi9xE3cve8E4vPOkI7H67uCrh rx39S2qTGY7WCjYZ0cg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-17_05,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 malwarescore=0 phishscore=0 spamscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603180061 Hi Dmitry , On 3/17/2026 8:42 PM, Dmitry Baryshkov wrote: > On Tue, Mar 17, 2026 at 02:50:40PM +0530, Harshal Dev wrote: >> Update the inline-crypto engine DT binding in a backward compatible manner >> to allow specifying up to two clocks along with their names and associated >> power-domain. > > This should come after the "why" part. Ack. > >> >> When the 'clk_ignore_unused' flag is not passed on the kernel command line >> occasional unclocked ICE hardware register access are observed when the >> kernel disables the unused 'iface' clock before ICE can probe. On the other >> hand, when the 'pd_ignore_unused' flag is not passed on the command line, >> clock 'stuck' issues are observed if the power-domain required by ICE >> hardware is unused and thus disabled before ICE probe could happen. > > You can simply say that ICE requires these clocks and these power > domains to function. Accessing the hardware can fail if they are > disabled by the kernel for whater reasons. > Ack. >> >> To avoid these scenarios, the 'iface' clock and the associated power-domain >> should be specified in the ICE device tree node and enabled by ICE. >> >> Fixes: f6ff91a47ac57 ("dt-bindings: crypto: Add Qualcomm Inline Crypto Engine") >> Signed-off-by: Harshal Dev >> --- >> .../bindings/crypto/qcom,inline-crypto-engine.yaml | 16 +++++++++++++++- >> 1 file changed, 15 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml >> index 876bf90ed96e..99c541e7fa8c 100644 >> --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml >> +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml >> @@ -30,6 +30,16 @@ properties: >> maxItems: 1 >> >> clocks: >> + minItems: 1 >> + maxItems: 2 >> + >> + clock-names: >> + minItems: 1 >> + items: >> + - const: core >> + - const: iface >> + >> + power-domains: >> maxItems: 1 >> >> operating-points-v2: true >> @@ -52,7 +62,11 @@ examples: >> compatible = "qcom,sm8550-inline-crypto-engine", >> "qcom,inline-crypto-engine"; >> reg = <0x01d88000 0x8000>; >> - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; >> + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, >> + <&gcc GCC_UFS_PHY_AHB_CLK>; >> + clock-names = "core", >> + "iface"; > > We don't actually need names here. You can use indices instead, making > the change completely backwards-compatible. > I do not have very concrete objections to this. But introducing the clock names isn't breaking backward compatibility either. I wanted to continue using the names since the ICE driver has been following the tradition of referring these clocks via names since it was part of the UFS/EMMC driver. This also helps me avoid touching the ICE driver source code for specifying the index of the clocks. Let me know if continuing to use the names is a no-go from you for some other reason. Thanks, Harshal >> + power-domains = <&gcc UFS_PHY_GDSC>; >> >> operating-points-v2 = <&ice_opp_table>; >> >> >> -- >> 2.34.1 >> >