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Tue, 25 Feb 2025 21:49:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IHPdfACxvty1eZQAAd+waUgWYZ9BRzhl4tvSNkf5vmOOGGL1MjuycVG4/ok6It6VJv1qusXfw== X-Received: by 2002:a17:903:8c5:b0:215:8d49:e2a7 with SMTP id d9443c01a7336-22307e72899mr92674525ad.50.1740548946222; Tue, 25 Feb 2025 21:49:06 -0800 (PST) Received: from [10.217.199.21] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2230a0a639dsm24128625ad.203.2025.02.25.21.49.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Feb 2025 21:49:05 -0800 (PST) Message-ID: <1b1e6e6a-84ee-4884-826b-f092ab5f3cf3@oss.qualcomm.com> Date: Wed, 26 Feb 2025 11:18:59 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: sm8750: Fix cluster hierarchy for idle states To: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jishnu Prakash , Raviteja Laggyshetty , Taniya Das , Melody Olvera Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_lsrao@quicinc.com References: <20250218-sm8750_cluster_idle-v1-1-5529df00f642@oss.qualcomm.com> <638f05f4-3a0e-459d-aec0-b925ca7f657c@oss.qualcomm.com> Content-Language: en-US From: "Maulik Shah (mkshah)" In-Reply-To: <638f05f4-3a0e-459d-aec0-b925ca7f657c@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 3a3ql4bT0db8RztIja2qyssTifMABthd X-Proofpoint-ORIG-GUID: 3a3ql4bT0db8RztIja2qyssTifMABthd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_08,2025-02-26_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 malwarescore=0 impostorscore=0 adultscore=0 priorityscore=1501 spamscore=0 mlxlogscore=872 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502260044 On 2/22/2025 1:21 AM, Konrad Dybcio wrote: > On 18.02.2025 7:58 AM, Maulik Shah wrote: >> SM8750 have two different clusters. cluster0 have CPU 0-5 as child and >> cluster1 have CPU 6-7 as child. Each cluster requires its own idle state >> and power domain in order to achieve complete domain sleep state. >> >> However only single cluster idle state is added mapping CPU 0-7 to the >> same power domain. Fix this by correctly mapping each CPU to respective >> cluster power domain and add domain idle state for cluster1. >> >> Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi") >> Signed-off-by: Maulik Shah >> --- >> arch/arm64/boot/dts/qcom/sm8750.dtsi | 36 +++++++++++++++++++++++++----------- >> 1 file changed, 25 insertions(+), 11 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..3af928be5b68b47988dd55f4add8e3712f07d5ab 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> @@ -178,7 +178,15 @@ cluster1_c4: cpu-sleep-1 { >> }; >> >> domain-idle-states { >> - cluster_cl5: cluster-sleep-0 { >> + cluster0_cl5: cluster-sleep-0 { >> + compatible = "domain-idle-state"; >> + arm,psci-suspend-param = <0x01000054>; >> + entry-latency-us = <2150>; >> + exit-latency-us = <1983>; >> + min-residency-us = <9144>; >> + }; > > I don't think this is necessary, you should be gtg with just creating the > new power domain for cluster 0/1 and pointing both to the same cluster idle > state (unless they both need different latency numbers > Sure, I will address this in v2. Thanks, Maulik > Konrad