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From: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
To: Chen Wang <unicorn_wang@outlook.com>,
	Inochi Amaoto <inochiama@outlook.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Chao Wei <chao.wei@sophgo.com>, Conor Dooley <conor@kernel.org>
Cc: "Albert Ou" <aou@eecs.berkeley.edu>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Daniel Lezcano" <daniel.lezcano@linaro.org>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Miquèl Raynal" <miquel.raynal@bootlin.com>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v4 4/4] riscv: dts: sophgo: Add LicheeRV Nano board device tree
Date: Fri, 30 Aug 2024 10:06:45 +0200	[thread overview]
Message-ID: <1b202582-0487-483c-ba80-47125551eb5d@bootlin.com> (raw)
In-Reply-To: <MA0P287MB2822AC58BC43FDE03802E773FE972@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM>

>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include "sg2002.dtsi"
>>> +
>>> +/ {
>>> +    model = "LicheeRV Nano B";
>>> +    compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", 
>>> "sophgo,sg2002";
>>> +
>>> +    aliases {
>>> +        gpio0 = &gpio0;
>>> +        gpio1 = &gpio1;
>>> +        gpio2 = &gpio2;
>>> +        gpio3 = &gpio3;
>>> +        serial0 = &uart0;
>>> +        serial1 = &uart1;
>>> +        serial2 = &uart2;
>>> +        serial3 = &uart3;
>>> +        serial4 = &uart4;
>>> +    };
>>> +
>>> +    chosen {
>>> +        stdout-path = "serial0:115200n8";
>>> +    };
>>> +};
>>> +
>>> +&osc {
>>> +    clock-frequency = <25000000>;
>>> +};
>>> +
>>> +&sdhci0 {
>>> +    status = "okay";
>>> +    bus-width = <4>;
>>> +    no-1-8-v;
>>> +    no-mmc;
>>> +    no-sdio;
>>> +    disable-wp;
>>> +};
>>> +
>>> +&uart0 {
>>> +    status = "okay";
>>> +};
>>> +
>>> +&uart1 {
>>> +    status = "okay";
>>> +};
>>> +
>>> +&i2c0 {
>>> +    status = "okay";
>>> +};
>>>
>>> -- 
>>> 2.45.2
>>>
>> Have you test you patch with a real board? Especially
>> for device "uart1" and "i2c0", I suspect your
>> configuartion does not work by default.
> 
> Hi, Thomas Bonnefille,
> 
> Can you please double check and feedback, I want to confirm this before 
> acking this change.
> 
> As you know, rc6 will come next week and I'm planning a pr next week.
> 
> Regards,
> 
> Chen
> 
Hello Chen and Inochi,

I'm really sorry, indeed, those nodes certainly don't work, it was a 
mistake on my side introduced between v1 and v2.
However, I can ensure that "uart0" and "sdhci0" are working fine.
May I suggest to remove those two nodes? I can send a new iteration if 
it's easier for you to handle?

  reply	other threads:[~2024-08-30  8:06 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-11 10:01 [PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano Thomas Bonnefille
2024-07-11 10:01 ` [PATCH v4 1/4] dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic Thomas Bonnefille
2024-07-30  6:34   ` Inochi Amaoto
2024-07-11 10:01 ` [PATCH v4 2/4] dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles Thomas Bonnefille
2024-07-11 10:01 ` [PATCH v4 3/4] riscv: dts: sophgo: Add initial SG2002 SoC device tree Thomas Bonnefille
2024-07-11 10:01 ` [PATCH v4 4/4] riscv: dts: sophgo: Add LicheeRV Nano board " Thomas Bonnefille
2024-08-29  5:52   ` Inochi Amaoto
2024-08-30  0:37     ` Chen Wang
2024-08-30  8:06       ` Thomas Bonnefille [this message]
2024-08-30  9:22         ` Chen Wang
2024-08-30 11:20         ` Inochi Amaoto
2024-09-04  1:02           ` Chen Wang
2024-07-12  0:31 ` [PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano Inochi Amaoto
2024-07-12  1:27 ` Chen Wang
2024-07-12  1:33 ` Chen Wang
2024-07-12 14:15   ` Conor Dooley
2024-07-13  0:13     ` Chen Wang
2024-08-26  2:55 ` Inochi Amaoto

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