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[104.129.187.94]) by smtp.gmail.com with ESMTPSA id f185sm1284523pfb.183.2019.10.08.23.29.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Oct 2019 23:30:00 -0700 (PDT) Subject: Re: [PATCH v10 1/3] arm64: cpufeature: introduce helper cpu_has_hw_af() To: Suzuki K Poulose , "Justin He (Arm Technology China)" , Marc Zyngier , Will Deacon Cc: Mark Rutland , "Kaly Xin (Arm Technology China)" , Catalin Marinas , "linux-kernel@vger.kernel.org" , Matthew Wilcox , "linux-mm@kvack.org" , James Morse , "linux-arm-kernel@lists.infradead.org" , Punit Agrawal , Thomas Gleixner , Andrew Morton , "Kirill A. Shutemov" References: <20190930015740.84362-1-justin.he@arm.com> <20190930015740.84362-2-justin.he@arm.com> <20191001125446.gknoofnm7az4wqf5@willie-the-truck> <20191001141848.762296bd@why> From: Jia He Message-ID: <1b28b20c-bc10-dbf6-aa78-afd985cf8920@gmail.com> Date: Wed, 9 Oct 2019 14:29:42 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Suzuki On 2019/10/8 23:32, Suzuki K Poulose wrote: > > > On 08/10/2019 02:12, Justin He (Arm Technology China) wrote: >> Hi Will and Marc >> Sorry for the late response, just came back from a vacation. >> >>> -----Original Message----- >>> From: Marc Zyngier >>> Sent: 2019年10月1日 21:19 >>> To: Will Deacon >>> Cc: Justin He (Arm Technology China) ; Catalin >>> Marinas ; Mark Rutland >>> ; James Morse ; >>> Matthew Wilcox ; Kirill A. Shutemov >>> ; linux-arm-kernel@lists.infradead.org; >>> linux-kernel@vger.kernel.org; linux-mm@kvack.org; Punit Agrawal >>> ; Thomas Gleixner ; >>> Andrew Morton ; hejianet@gmail.com; Kaly >>> Xin (Arm Technology China) >>> Subject: Re: [PATCH v10 1/3] arm64: cpufeature: introduce helper >>> cpu_has_hw_af() >>> >>> On Tue, 1 Oct 2019 13:54:47 +0100 >>> Will Deacon wrote: >>> >>>> On Mon, Sep 30, 2019 at 09:57:38AM +0800, Jia He wrote: >>>>> We unconditionally set the HW_AFDBM capability and only enable it on >>>>> CPUs which really have the feature. But sometimes we need to know >>>>> whether this cpu has the capability of HW AF. So decouple AF from >>>>> DBM by new helper cpu_has_hw_af(). >>>>> >>>>> Signed-off-by: Jia He >>>>> Suggested-by: Suzuki Poulose >>>>> Reviewed-by: Catalin Marinas >>>>> --- >>>>>   arch/arm64/include/asm/cpufeature.h | 10 ++++++++++ >>>>>   1 file changed, 10 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/include/asm/cpufeature.h >>> b/arch/arm64/include/asm/cpufeature.h >>>>> index 9cde5d2e768f..949bc7c85030 100644 >>>>> --- a/arch/arm64/include/asm/cpufeature.h >>>>> +++ b/arch/arm64/include/asm/cpufeature.h >>>>> @@ -659,6 +659,16 @@ static inline u32 >>> id_aa64mmfr0_parange_to_phys_shift(int parange) >>>>>    default: return CONFIG_ARM64_PA_BITS; >>>>>    } >>>>>   } >>>>> + >>>>> +/* Check whether hardware update of the Access flag is supported */ >>>>> +static inline bool cpu_has_hw_af(void) >>>>> +{ >>>>> + if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM)) >>>>> +         return read_cpuid(ID_AA64MMFR1_EL1) & 0xf; >>>> >>>> 0xf? I think we should have a mask in sysreg.h for this constant. >>> >>> We don't have the mask, but we certainly have the shift. >>> >>> GENMASK(ID_AA64MMFR1_HADBS_SHIFT + 3, >>> ID_AA64MMFR1_HADBS_SHIFT) is a bit >>> of a mouthful though. Ideally, we'd have a helper for that. >>> >> Ok, I will implement the helper if there isn't so far. >> And then replace the 0xf with it. > > Or could we simpl reuse existing cpuid_feature_extract_unsigned_field() ? > > u64 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); > > return cpuid_feature_extract_unsigned_field(mmfr1, ID_AA64MMFR1_HADBS_SHIFT) ? > Yes, we can, I will send the new version --- Cheers, Justin (Jia He)