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Mon, 08 Jul 2024 07:47:33 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 4687lV2H006833 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 8 Jul 2024 07:47:31 GMT Received: from [10.239.132.204] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 8 Jul 2024 00:47:09 -0700 Message-ID: <1b32168b-7d1c-4b18-b4f3-a4979232b515@quicinc.com> Date: Mon, 8 Jul 2024 15:47:06 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 00/47] arm64: qcom: dts: add QCS9100 support To: Conor Dooley , Krzysztof Kozlowski CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , References: <20240703025850.2172008-1-quic_tengfan@quicinc.com> <20240703035735.2182165-1-quic_tengfan@quicinc.com> <7417fd8c-e852-45ee-bac9-d92921036e2f@kernel.org> <20240703-manager-armless-b13b18c79192@wendy> From: Tengfei Fan In-Reply-To: <20240703-manager-armless-b13b18c79192@wendy> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: WJaCcFF2njxbbZhKA7uiH0ECQvUaDd6U X-Proofpoint-GUID: WJaCcFF2njxbbZhKA7uiH0ECQvUaDd6U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-08_02,2024-07-05_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 bulkscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 mlxlogscore=999 malwarescore=0 mlxscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407080059 On 7/3/2024 2:28 PM, Conor Dooley wrote: > On Wed, Jul 03, 2024 at 06:45:00AM +0200, Krzysztof Kozlowski wrote: >> On 03/07/2024 05:56, Tengfei Fan wrote: >>> Introduce support for the QCS9100 SoC device tree (DTSI) and the >>> QCS9100 RIDE board DTS. The QCS9100 is a variant of the SA8775p. >>> While the QCS9100 platform is still in the early design stage, the >>> QCS9100 RIDE board is identical to the SA8775p RIDE board, except it >>> mounts the QCS9100 SoC instead of the SA8775p SoC. >> >> The same huge patchset, to huge number of recipients was sent twice. >> First, sorry, this is way too big. Second, it has way too many >> recipients, but this is partially a result of first point. Only >> partially because you put here dozen of totally unrelated emails. Sorry, >> that does not make even sense. See form letter at the end how this >> works. Third, sending it to everyone twice is a way to annoy them off >> twice... Fourth, >> >> Please split your work and do not cc dozen of unrelated folks. > > One of the extra recipients is cos that of that patch I sent adding the > cache bindings to the cache entry, forgetting that that would CC the > riscv list on all cache bindings. I modified that patch to drop the riscv > list from the entry. > > Cheers, > Conor. Thank you, Conor! -- Thx and BRs, Tengfei Fan