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Thu, 23 Jan 2025 21:32:04 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50NLW32e001485 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Jan 2025 21:32:03 GMT Received: from [10.110.95.241] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 23 Jan 2025 13:32:03 -0800 Message-ID: <1b429f3f-2fff-45bb-86dd-48b1d164ccc8@quicinc.com> Date: Thu, 23 Jan 2025 13:32:02 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 18/35] drm/msm/dpu: get rid of DPU_PINGPONG_DSC To: Dmitry Baryshkov , Rob Clark , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio CC: , , , References: <20241214-dpu-drop-features-v1-0-988f0662cb7e@linaro.org> <20241214-dpu-drop-features-v1-18-988f0662cb7e@linaro.org> Content-Language: en-US From: Abhinav Kumar In-Reply-To: <20241214-dpu-drop-features-v1-18-988f0662cb7e@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KvIfi-9qKNkBUJtuA6rLf0wWNX-6O2pE X-Proofpoint-GUID: KvIfi-9qKNkBUJtuA6rLf0wWNX-6O2pE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-23_09,2025-01-23_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 spamscore=0 impostorscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501230155 On 12/13/2024 2:14 PM, Dmitry Baryshkov wrote: > Continue migration to the MDSS-revision based checks and replace > DPU_PINGPONG_DSC feature bit with the core_major_ver < 7 check. > > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 2 -- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 2 -- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 6 ++---- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 10 ++-------- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 2 +- > 7 files changed, 5 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c > index 36c0ec775b92036eaab26e1fa5331579651ac27c..49e03ecee9e8b567a3f809b977deb83731006ac0 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c > @@ -319,7 +319,7 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(struct drm_device *dev, > c->ops.disable_autorefresh = dpu_hw_pp_disable_autorefresh; > } > > - if (test_bit(DPU_PINGPONG_DSC, &cfg->features)) { > + if (mdss_rev->core_major_ver < 7) { > c->ops.setup_dsc = dpu_hw_pp_setup_dsc; > c->ops.enable_dsc = dpu_hw_pp_dsc_enable; > c->ops.disable_dsc = dpu_hw_pp_dsc_disable; > So far in this series, we replaced the feature bits with >= checks of core_revisions. That kind of works as usually feature bits get added after a specific version. With this patch and later, whenever we use < checks it gets a bit tricky as we might also need an upper bound. Feature bits gave individual control of chipsets but generalizing that all chipsets < 7 have PP DSC is also not correct. I have to really cross-check but there could be some old chipsets which do not have DSC at all.