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Sat, 22 Jun 2024 01:54:27 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45M1sQpL027220 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 22 Jun 2024 01:54:26 GMT Received: from [10.110.82.141] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 21 Jun 2024 18:54:22 -0700 Message-ID: <1b4d1aaa-ae5f-a6ed-d6b3-e922e84c3d84@quicinc.com> Date: Fri, 21 Jun 2024 18:54:19 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [RFC PATCH 1/4] drm/msm: register a fault handler for display mmu faults Content-Language: en-US To: Stephen Boyd , Daniel Vetter , "David Airlie" , Dmitry Baryshkov , Marijn Suijten , Rob Clark , Sean Paul , CC: , , , , , References: <20240517233801.4071868-1-quic_abhinavk@quicinc.com> <20240517233801.4071868-2-quic_abhinavk@quicinc.com> From: Abhinav Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: DWD4KbIIgwdZwq4WBnH8jD_rBnK-aeNi X-Proofpoint-ORIG-GUID: DWD4KbIIgwdZwq4WBnH8jD_rBnK-aeNi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-21_12,2024-06-21_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 adultscore=0 mlxscore=0 suspectscore=0 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406220009 On 5/20/2024 9:12 PM, Stephen Boyd wrote: > Quoting Abhinav Kumar (2024-05-17 16:37:56) >> diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c >> index af6a6fcb1173..62c8e6163e81 100644 >> --- a/drivers/gpu/drm/msm/msm_kms.c >> +++ b/drivers/gpu/drm/msm/msm_kms.c >> @@ -200,6 +200,28 @@ struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev) >> return aspace; >> } >> >> +static int msm_kms_fault_handler(void *arg, unsigned long iova, int flags, void *data) >> +{ >> + struct msm_kms *kms = arg; >> + struct msm_disp_state *state; >> + int ret; >> + >> + ret = mutex_lock_interruptible(&kms->dump_mutex); > > From past experience I've seen the smmu fault handler called in hardirq > context, so it can't sleep. Is there some way to grab the register > contents without sleeping? Otherwise this will have to fork off > somewhere else that can take locks, runtime PM resume, etc. > Sorry for the delay in this series. Yes, this is a valid point. Let me see move to msm_disp_snapshot_state() as that one will spawn a kthread then dump the registers. >> + if (ret) >> + return ret; >> + >> + state = msm_disp_snapshot_state_sync(kms); >> + >> + mutex_unlock(&kms->dump_mutex); >> +