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[192.35.156.11]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b55396db81fsm9565146a12.19.2025.09.23.14.51.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Sep 2025 14:51:18 -0700 (PDT) Message-ID: <1b51550f-90db-2ead-0ec5-93ce786ffdff@oss.qualcomm.com> Date: Tue, 23 Sep 2025 14:51:16 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 2/9] dt-bindings: phy: qcom,qmp-usb: Add Glymur USB UNI PHY compatible Content-Language: en-US To: Johan Hovold Cc: Dmitry Baryshkov , krzk+dt@kernel.org, conor+dt@kernel.org, kishon@kernel.org, vkoul@kernel.org, gregkh@linuxfoundation.org, robh@kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-phy@lists.infradead.org References: <20250920032108.242643-1-wesley.cheng@oss.qualcomm.com> <20250920032108.242643-3-wesley.cheng@oss.qualcomm.com> <7gvp6pshp4eiugk3qodg2ub3azu365loturidbkxqly6nhtgq7@bxnkxeqzarkv> <4116b593-d36d-df10-6101-4e3539b8b812@oss.qualcomm.com> From: Wesley Cheng In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: DOYBEBD9sPArY8EudjZ0LU-y-DMN-baY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAxOCBTYWx0ZWRfX60EN6S4Q0+8W 8Bg+Wbi1oLl8g+xOVvEFRcfLUO9Dk9hP0Uz0xLP+dLiVzkqzVPY9jUHHnnPF9rOKbSZyw9sAwv6 z5LLxBlJEIyMsdlVZdz0azN4JR8+zP4sY/j5vHi6+FRFyJ6wVzksuqbS7gtgjxev6WaQTB+kok3 ZQ1mDQ6e08jMYuF7IATpByhqhXP57zQ18m2jGbnrHUM2zXjppoNy7LGxzbZCYKWZ3Fti+zjLosf vgiDs+ZBmbcQ6TlASl8GX9qfkinLgTD34oAWeOTiZsnnmjRHOhw5ej/sVBzEUPdM5iGHSoUOojO ZfAQFarB4psY0ZNqMenn5U/EJFS0lpymbbFZ2vEJUXLWeeXoqzFfNm+a9yTr2+5+hl5Bk00yRg1 bH8uAtTr X-Proofpoint-ORIG-GUID: DOYBEBD9sPArY8EudjZ0LU-y-DMN-baY X-Authority-Analysis: v=2.4 cv=Dp1W+H/+ c=1 sm=1 tr=0 ts=68d31658 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ZdW6uxA9NKXbfdqeeS2OGA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=VwQbUJbxAAAA:8 a=zitRP-D0AAAA:8 a=A-OFauQzm6gaq6ZTC9UA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=xwnAI6pc5liRhupp6brZ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-23_06,2025-09-22_05,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 adultscore=0 bulkscore=0 impostorscore=0 phishscore=0 spamscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200018 On 9/23/2025 12:27 AM, Johan Hovold wrote: > On Mon, Sep 22, 2025 at 06:00:04PM -0700, Wesley Cheng wrote: >> >> >> On 9/20/2025 8:22 AM, Dmitry Baryshkov wrote: >>> On Fri, Sep 19, 2025 at 08:21:01PM -0700, Wesley Cheng wrote: >>>> The Glymur USB subsystem contains a multiport controller, which utilizes >> >>> two QMP UNI PHYs. Add the proper compatible string for the Glymur SoC. >>>> @@ -16,6 +16,7 @@ description: >>>> properties: >>>> compatible: >>>> enum: >>>> + - qcom,glymur-qmp-usb3-uni-phy > > Odd indentation? > >>>> - qcom,ipq5424-qmp-usb3-phy >>>> - qcom,ipq6018-qmp-usb3-phy >>>> - qcom,ipq8074-qmp-usb3-phy >>>> @@ -62,6 +63,8 @@ properties: >>>> >>>> vdda-pll-supply: true >>>> >>>> + refgen-supply: true >>> >>> You've added it, but it's not referenced as required. Why is it so? > >> The refgen clock isn't always required on each and every platform unlike >> the .9v and 1.2v rail/supply, which directly power the QMP PHY. It only >> really depends on how the refclk/CXO network is built for that >> particular chipset. The refgen ensures that we're properly voting for >> the supply that is powering our CXO buffer. > > I thought we discussed this before and concluded that this is not an > accurate description of the hardware (even if you now call this supply > refgen instead of qref): Hi Johan, refgen and qrefs are different things. I will try to clarify as much as I can from the discussion you linked below. (based on my understanding of the reference clock network) The refgen is the main supply that controls the reference clock (CXO) into a specific branch. Within each of these branches there are clock repeaters that are supplied by QREFs, and is basically the supply to the clkref switch controlled by the TCSR registers. The way some of the tech blocks are connected, the QREFs/refgen may share the same regulator as some of the PHY's core supply. Some may not even have QREFs at all. One example is the QMP PHY that is associated to the primary controller on Glymur. It has a refgen regulator, but no QREFs, hence we only need to vote the refgen accordingly. I don't know if that helps you understand it a bit more to convince you of the new regulator addition. If anything we may need to add an explicit QREF supply also :). Thanks Wesley Cheng > > https://lore.kernel.org/lkml/aEBfV2M-ZqDF7aRz@hovoldconsulting.com/ > > Given your description above this still looks wrong (at least after a > quick look). > > Johan