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Add the optional > 'interconnects' property to the binding to allow platform DT nodes > to describe this path. > > Signed-off-by: Bibek Kumar Patro > --- > .../devicetree/bindings/iommu/arm,smmu.yaml | 27 ++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index 06fb5c8e7547cb7a92823adc2772b94f747376a6..3a677ff1a18fcdf5c0ca9ec8a017d41f9eb5ff09 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -243,6 +243,13 @@ properties: > minItems: 1 > maxItems: 3 > > + interconnects: > + maxItems: 1 > + description: > + Interconnect path to the SMMU register space. Required on SoCs > + where the SMMU registers are only accessible after a bandwidth > + vote has been placed on the interconnect fabric. > + > nvidia,memory-controller: > description: | > A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. > @@ -602,6 +609,26 @@ allOf: > clock-names: false > clocks: false > > + - if: > + properties: > + compatible: > + items: > + - enum: > + - qcom,qcs615-smmu-500 > + - qcom,qcs8300-smmu-500 > + - qcom,sa8775p-smmu-500 > + - qcom,sc7280-smmu-500 This is a list of targets that happen to be supported by QLI.. but should this list not contain _all_ Qualcomm SoCs, or at least a much broader range? Perhaps if: properties: compatible: contains: qcom,adreno-smmu ? Konrad