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Tue, 22 Jul 2025 12:56:02 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEJK019g6DqECaNDbpD0Yvmal8JjGmdWP1kCx05y6YQEB+NqSgr5xgmvBvu9sxGV/5wQFRvhg== X-Received: by 2002:a05:6a00:92a7:b0:736:31cf:2590 with SMTP id d2e1a72fcca58-760353f2759mr687654b3a.16.1753214161634; Tue, 22 Jul 2025 12:56:01 -0700 (PDT) Received: from [192.168.1.4] ([106.222.235.133]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-759cbc680absm8266052b3a.144.2025.07.22.12.55.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Jul 2025 12:56:01 -0700 (PDT) Message-ID: <1b7817eb-6d54-4ed0-9ab3-d5b521d5bf6d@oss.qualcomm.com> Date: Wed, 23 Jul 2025 01:25:56 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 04/17] drm/msm/a6xx: Poll additional DRV status To: Dmitry Baryshkov Cc: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250720-ifpc-support-v1-0-9347aa5bcbd6@oss.qualcomm.com> <20250720-ifpc-support-v1-4-9347aa5bcbd6@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 4NMhMI7EUHq47BVRVrfTqcvqqhGAvbNR X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDE3MCBTYWx0ZWRfX404krhkJ5fWV DDuBaCmdTgO2znv5ib36hDpg/wGqXsDt6vuEqB7AAkD/NFCzgnqvLL+NTSbNuABE15fRxxLM98E JSS2TpP1KYj2SKFpurweURR5nOls1U4Cc4aEXHQ3AXGHJm/fwyBn2/LWFhZYNzeV6aPWI435/g0 MXyGsqEZUgdcFuOPZK9fKoT7Wu1RQV2smX9sb6NTKmEYuIMRJ0d4U1OzHV4l+JJ2yF1SUYaJaAE bp8HnJLJrp+0n51mHhW5MhyH1M86YCYeIdWTkzWPRI9nuC5iILKp+xAiCy0AxP0Xcrc4HYXVPhQ q5WKnDW1CvS8b1OvFN9xg6R/Dctq+0B7tr5ZH57HziMcvE4tTbUjflYYoyMX/57DoHRjiaZflNn /sk2Rk832sREjJ0yU0Uvz+HVQRuhaFyoxyqyFHnok72COmVr2pOw0dQ4M/+x3TOoJ+O2CKDO X-Authority-Analysis: v=2.4 cv=E8/Npbdl c=1 sm=1 tr=0 ts=687fecd3 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=4dphQItTPUswyQvINXrzgA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=TSBj-XRfAaQ4HSZEJ1QA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: 4NMhMI7EUHq47BVRVrfTqcvqqhGAvbNR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 suspectscore=0 clxscore=1015 phishscore=0 mlxlogscore=999 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220170 On 7/22/2025 7:01 PM, Dmitry Baryshkov wrote: > On Sun, Jul 20, 2025 at 05:46:05PM +0530, Akhil P Oommen wrote: >> A7XX_GEN2 generation has additional TCS slots. Poll the respective >> DRV status registers before pm suspend. >> > > Fixes? Ack. Will add the tag. It is good to ensure there are no outstanding votes. -Akhil > >> Signed-off-by: Akhil P Oommen >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> index 790ef2f94a0b0cd40433d7edb6a89e4f04408bf5..3bebb6dd7059782ceca29f2efd2acee24d3fc930 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> @@ -987,6 +987,22 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) >> val, (val & 1), 100, 10000); >> gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, >> val, (val & 1), 100, 1000); >> + >> + if (!adreno_is_a740_family(adreno_gpu)) >> + return; >> + >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS4_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS5_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS6_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS7_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 1000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS8_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS9_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 1000); >> } >> >> /* Force the GMU off in case it isn't responsive */ >> >> -- >> 2.50.1 >> >