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From: Stefan Agner <stefan@agner.ch>
To: Marc Kleine-Budde <mkl@pengutronix.de>
Cc: shawn.guo@freescale.com, kernel@pengutronix.de,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 4/4] can: flexcan: add vf610 support for FlexCAN
Date: Wed, 16 Jul 2014 08:43:22 +0200	[thread overview]
Message-ID: <1b8a8ca03b4a160027a79b722f697e25@agner.ch> (raw)
In-Reply-To: <53C5398F.2000005@pengutronix.de>

Am 2014-07-15 16:24, schrieb Marc Kleine-Budde:
<snip>
>> @@ -150,18 +171,20 @@
>>   * FLEXCAN hardware feature flags
>>   *
>>   * Below is some version info we got:
>> - *    SOC   Version   IP-Version  Glitch-  [TR]WRN_INT
>> - *                                Filter?   connected?
>> - *   MX25  FlexCAN2  03.00.00.00     no         no
>> - *   MX28  FlexCAN2  03.00.04.00    yes        yes
>> - *   MX35  FlexCAN2  03.00.00.00     no         no
>> - *   MX53  FlexCAN2  03.00.00.00    yes         no
>> - *   MX6s  FlexCAN3  10.00.12.00    yes        yes
>> + *    SOC   Version   IP-Version  Glitch-  [TR]WRN_INT  Memory err
>> + *                                Filter?   connected?  detection
>> + *   MX25  FlexCAN2  03.00.00.00     no         no         no
>> + *   MX28  FlexCAN2  03.00.04.00    yes        yes         no
>> + *   MX35  FlexCAN2  03.00.00.00     no         no         no
>> + *   MX53  FlexCAN2  03.00.00.00    yes         no         no
>> + *   MX6s  FlexCAN3  10.00.12.00    yes        yes         no
>> + *   VF610 FlexCAN3  ?               no         no        yes
>                                         ^^         ^^
> 
> Can you check the datasheet if the flexcan core has a "Glitch Filter
> Width Register (FLEXCANx_GFWR)"


There is no such register called GFWR/Glitch Filter or similar.

> Can you check if the core generates a warning interrupt with the current
> setup, if you don't switch on bus error reporting? This means internally
> the [TR]WRN_INT is connected and works as specified.

Ok, so I disabled TWRNMSK (Bit 11) in the control register and printed
out the error and status register (ESR1), this is what I get:
[  191.285295] flexcan_irq, esr=00040080
[  191.288996] flexcan_irq, ctrl=17092051

Bit 17 (TWRNINT) is not set while TWRNMSK is disabled. Hence [TR]WRN_INT
is not connected?


--
Stefan

  reply	other threads:[~2014-07-16  6:43 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-07-15 12:56 [PATCH v3 0/4] ARM: vf610: add FlexCAN support Stefan Agner
2014-07-15 12:56 ` [PATCH v3 1/4] ARM: dts: vf610: add FlexCAN node Stefan Agner
2014-07-15 12:56 ` [PATCH v3 2/4] ARM: imx: clk-vf610: fix FlexCAN clock gating Stefan Agner
2014-07-15 12:56 ` [PATCH v3 3/4] can: flexcan: switch on clocks before accessing ecr register Stefan Agner
2014-07-15 13:54   ` Lothar Waßmann
2014-07-15 13:57     ` Marc Kleine-Budde
2014-07-15 12:56 ` [PATCH v3 4/4] can: flexcan: add vf610 support for FlexCAN Stefan Agner
2014-07-15 14:24   ` Marc Kleine-Budde
2014-07-16  6:43     ` Stefan Agner [this message]
2014-07-25 10:50       ` Stefan Agner
2014-07-25 13:33         ` Marc Kleine-Budde
2014-07-28 16:20           ` Stefan Agner
2014-07-28 16:28             ` Marc Kleine-Budde
2014-07-29  7:29               ` Stefan Agner
2014-07-30 11:47                 ` Marc Kleine-Budde
2014-08-04 13:43                   ` Stefan Agner
2014-08-04 14:27                     ` Marc Kleine-Budde
2014-08-04 16:01                       ` Stefan Agner
2014-08-05  9:52                         ` Marc Kleine-Budde
2014-08-05 12:38                           ` Stefan Agner
2014-08-14 10:38                         ` Marc Kleine-Budde
2014-07-28 16:31             ` Marc Kleine-Budde
2014-07-15 13:54 ` [PATCH v3 0/4] ARM: vf610: add FlexCAN support Marc Kleine-Budde
2014-08-14 10:04   ` Marc Kleine-Budde
2014-07-16  6:11 ` Shawn Guo

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