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Wed, 28 Jan 2026 12:56:06 -0600 Received: from [172.24.233.254] (santhoshkumark.dhcp.ti.com [172.24.233.254]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 60SIu1IW2854453; Wed, 28 Jan 2026 12:56:02 -0600 Message-ID: <1b9569c6-5073-439d-b0b3-99a5a40841f6@ti.com> Date: Thu, 29 Jan 2026 00:26:00 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 00/15] spi: cadence-qspi: Add Renesas RZ/N1 support To: "Miquel Raynal (Schneider Electric)" , "Mark Brown" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Geert Uytterhoeven" , Magnus Damm , Vaishnav Achath CC: Thomas Petazzoni , =?UTF-8?Q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Pratyush Yadav , Pascal Eberhard , , , , , References: <20260122-schneider-6-19-rc1-qspi-v4-0-f9c21419a3e6@bootlin.com> Content-Language: en-US From: Santhosh Kumar K In-Reply-To: <20260122-schneider-6-19-rc1-qspi-v4-0-f9c21419a3e6@bootlin.com> Content-Type: text/plain; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jan 2026 18:56:08.9190 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fd009a14-5136-46c0-4b9b-08de5e9ee608 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004688.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR10MB5014 Hello Miquel, On 22/01/26 20:43, Miquel Raynal (Schneider Electric) wrote: > Hello, > > This series adds support for the QSPI controller available on Renesas > RZ/N1S and RZ/N1D SoC. It has been tested with a custom board (see last > SPI patch for details), but has been tested by Wolfram (thank you!) on > the DB board. > Link: https://lore.kernel.org/linux-devicetree/20260116114852.52948-2-wsa+renesas@sang-engineering.com/ > > Adding support for this SoC required a few adaptations in the Cadence > QSPI driver. The bulk of the work is in the few last patches. Everything > else is just misc style fixes and improvements which bothered me while I > was wandering. > > In order to support all constraints, I sometimes used a new quirk (for > the write protection feature and the "no indirect mode"), and sometimes > used the compatible directly. The ones I thought might not be RZ/N1 > specific have been implemented under the form of a quirk, in order to > ease their reuse. The other adaptations, which I believe are more > Renesas specific, have been handled using the compatible. This is all > very arbitrary, and can be discussed. > > Thanks, > Miquèl > > Signed-off-by: Miquel Raynal (Schneider Electric) Thank you for the series! Tested it on TI's AM62A SK (OSPI NAND flash) and AM62P SK (OSPI NOR flash). Tested-by: Santhosh Kumar K > --- > Changes in v4: > - Drop two binding patches judged useless. > - Collected Rob's acks. > - Fixed the RZ/N1D400 DTSI (removed the properties no longer relevant > after my binding changes). > - Link to v3: https://lore.kernel.org/r/20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com > > Changes in v3: > - Collected tags from Wolfram and Geert. > - Dropped the Cadence compatible as this fallback would simply not work > alone. > - Fixed the clock issue reported by Santhosh. > - Fixed the DT snippet following the discussion with Geert. > - Modified more deeply the binding, to no longer expect a fifo > size/depth nor any trigger address, as these values have no meaning in > the score of the Renesas implementation. > - Link to v2: https://lore.kernel.org/r/20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com > > Changes in v2: > - Fix commit log of DT binding patch, following Krzysztof's comment. > - Fix properties order in DTSI. > - Rebase on top of spi/for-next and fix all conflicts. > - Simplify even further the code in the cleanup patches following > Pratyush's advices. > - Link to v1: https://lore.kernel.org/r/20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com > > --- > Miquel Raynal (Schneider Electric) (15): > spi: dt-bindings: cdns,qspi-nor: Drop label in example > spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list > spi: cadence-qspi: Align definitions > spi: cadence-qspi: Fix style and improve readability > spi: cadence-qspi: Fix ORing style and alignments > spi: cadence-qspi: Remove an useless operation > spi: cadence-qspi: Make sure we filter out unsupported ops > spi: cadence-qspi: Fix probe error path and remove > spi: cadence-qspi: Try hard to disable the clocks > spi: cadence-qspi: Kill cqspi_jh7110_clk_init > spi: cadence-qspi: Add a flag for controllers without indirect access support > spi: cadence-qspi: Make sure write protection is disabled > spi: cadence-qspi: Use a default value for cdns,fifo-width > spi: cadence-qspi: Add support for the Renesas RZ/N1 controller > ARM: dts: r9a06g032: Describe the QSPI controller > > .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 35 ++- > arch/arm/boot/dts/renesas/r9a06g032.dtsi | 12 + > drivers/spi/spi-cadence-quadspi.c | 279 ++++++++++----------- > 3 files changed, 177 insertions(+), 149 deletions(-) > --- > base-commit: 7a3f3fdb79a26125b38fb91b68dab298ca7b44e0 > change-id: 20251219-schneider-6-19-rc1-qspi-7c3e1547af6d > > Best regards,