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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a21c050sm2186769866b.104.2025.08.12.04.51.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Aug 2025 04:51:31 -0700 (PDT) Message-ID: <1ba08f18-cfba-40f3-b600-1b1762e8982c@oss.qualcomm.com> Date: Tue, 12 Aug 2025 13:51:28 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V1 2/3] arm64: dts: qcom: sm8650: Enable MCQ support for UFS controller To: Manivannan Sadhasivam , Krzysztof Kozlowski Cc: Ram Kumar Dwivedi , alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250730082229.23475-1-quic_rdwivedi@quicinc.com> <20250730082229.23475-3-quic_rdwivedi@quicinc.com> <40ace3bc-7e5d-417a-b51a-148c5f498992@quicinc.com> <2a7bf809-73d9-4cb6-bcc9-3625ef1eb1fa@kernel.org> <5a32e933-03b9-4cc3-914c-46bdb2cedce6@kernel.org> <54gttzkpxg55vrh5wsvyvteovki377w3yjfejjddpzzrvldwkg@p7sc4knnvla3> <4fa9074e-609a-42aa-975a-a6daa7dd6d42@kernel.org> <5se3wgpfabzlcidflef5orwtl62jk2dtg4lx47gnqcqn7mya46@i6zir5uny7gi> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <5se3wgpfabzlcidflef5orwtl62jk2dtg4lx47gnqcqn7mya46@i6zir5uny7gi> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: igTtVaqFjRCwqMRT48DEjoxg1dGzOzlS X-Proofpoint-ORIG-GUID: igTtVaqFjRCwqMRT48DEjoxg1dGzOzlS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA2OCBTYWx0ZWRfX1SKuNQcrxRZG F4rr08ppLTGFiezGLO9axnle3lu+2ftgBRmO0Nwse7ElWPGBkJ59tvRaOxRSZ5AwDuvY/ZR30bu PYPDcQTuzFUFfLZYPk/qzLO07FU160tH+q0uGd5r3uuhjB604qmCfdhuxuvTKMnfR0rOdV1Wvqy xSoYdHtdk/Mq5w0Dy5lX4PvyHQqx7q+uQi8olz5rUxd7XeWjkW/Gy/8LpHbCEm7UL0XUTEgmhVf z2HKGE8y0lPbT/vp5WFyabbsVuIzu5OnHyaZIP2fhxwMZrrByTUzrezAldcFr+XHHMcYkPvoxyK MKVL/xvJFKyGTuCnBdFbVcLaGe9NG2e8m8T8t4BvvsWoj+wUD0KFY6iI3jeN4ZHLSIiX8P+Ma+h x0XsrCYx X-Authority-Analysis: v=2.4 cv=YMafyQGx c=1 sm=1 tr=0 ts=689b2ac5 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=ZRovytJ3VJirhm_mrpIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_06,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 priorityscore=1501 spamscore=0 suspectscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110068 On 8/11/25 11:27 AM, Manivannan Sadhasivam wrote: > On Fri, Aug 01, 2025 at 06:09:18PM GMT, Krzysztof Kozlowski wrote: >> On 01/08/2025 17:33, Manivannan Sadhasivam wrote: >>> On Fri, Aug 01, 2025 at 04:20:37PM GMT, Krzysztof Kozlowski wrote: >>>> On 01/08/2025 14:24, Manivannan Sadhasivam wrote: >>>>> On Thu, Jul 31, 2025 at 10:38:56AM GMT, Krzysztof Kozlowski wrote: >>>>>> On 31/07/2025 10:34, Ram Kumar Dwivedi wrote: >>>>>>> >>>>>>> >>>>>>> On 31-Jul-25 12:15 PM, Krzysztof Kozlowski wrote: >>>>>>>> On 30/07/2025 10:22, Ram Kumar Dwivedi wrote: >>>>>>>>> Enable Multi-Circular Queue (MCQ) support for the UFS host controller >>>>>>>>> on the Qualcomm SM8650 platform by updating the device tree node. This >>>>>>>>> includes adding new register regions and specifying the MSI parent >>>>>>>>> required for MCQ operation. >>>>>>>>> >>>>>>>>> MCQ is a modern queuing model for UFS that improves performance and >>>>>>>>> scalability by allowing multiple hardware queues. >>>>>>>>> >>>>>>>>> Changes: >>>>>>>>> - Add reg entries for mcq_sqd and mcq_vs regions. >>>>>>>>> - Define reg-names for the new regions. >>>>>>>>> - Specify msi-parent for interrupt routing. >>>>>>>>> >>>>>>>>> Signed-off-by: Ram Kumar Dwivedi >>>>>>>>> --- >>>>>>>>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 9 ++++++++- >>>>>>>>> 1 file changed, 8 insertions(+), 1 deletion(-) >>>>>>>>> >>>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>>>>>>>> index e14d3d778b71..5d164fe511ba 100644 >>>>>>>>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >>>>>>>>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>>>>>>>> @@ -3982,7 +3982,12 @@ ufs_mem_phy: phy@1d80000 { >>>>>>>>> >>>>>>>>> ufs_mem_hc: ufshc@1d84000 { >>>>>>>>> compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; >>>>>>>>> - reg = <0 0x01d84000 0 0x3000>; >>>>>>>>> + reg = <0 0x01d84000 0 0x3000>, >>>>>>>>> + <0 0x01da5000 0 0x2000>, >>>>>>>>> + <0 0x01da4000 0 0x0010>; >>>>>>>> >>>>>>>> >>>>>>>> These are wrong address spaces. Open your datasheet and look there. >>>>>>>> >>>>>>> Hi Krzysztof, >>>>>>> >>>>>>> I’ve reviewed it again, and it is correct and functioning as expected both on our upstream and downstream codebase. >>>>>>> I think it is probably overlooked by you. Can you please double check from your end? >>>>>>> >>>>>> >>>>>> No, it is not overlooked. There is no address space of length 0x10 at >>>>>> 0x01da4000 in qcom doc/datasheet system. Just open the doc and look >>>>>> there by yourself. The size is 0x15000. >>>>>> >>>>> >>>>> The whole UFS MCQ region is indeed of size 0x15000, but the SQD and VS registers >>>>> are at random offsets, not fixed across the SoC revisions. And there are some >>>>> big holes within the whole region for things like ICE and all. >>>>> >>>>> So it makes sense to map only the part of these regions and leave the unused >>>>> ones. >>>> Each item in the reg represents some continuous, dedicated address >>>> space, not individual registers or artificially decided subsection. The >>>> holes in such address space is not a problem, we do it all the time for >>>> all other devices as well. >>>> >>>> You need to use the definition of that address space. >>>> >>> >>> What if some of the registers in that whole address space is shared with other >>> peripherals such as ICE? >> >> >> It will be a different address space. We don't talk about imaginary >> 3rd-party SoC. Qualcomm datasheet lists address spaces in very precise >> way. We were recently fixing all address spaces for remoterpocs based on >> that. >> >>> >>> I agree with the fact that artifically creating separate register spaces leads >>> to issues, but here I'm worried about hardcoding the offsets in the driver which >>> can change between SoCs and also the shared address space with ICE. >> >> Drivers are expected to hard-code offsets and all drivers do it. Look at >> display, sound codecs (both SoC and soundwire devices). Everything >> hard-coded offsets internal to address space. >> >> What you essentially want is (making it border case) "reg" per register. >> > > I was worried about the ICE overlap, but I got access to the documentation and > verified myself (also with Nitin) that there is no ICE overlap. So yes, we can > map the entire MCQ region and live with the hardcoded offsets. (that means we can look into ripping out lots of code from the ufs driver as I attempted to before, feel free to take the wheel on that though) Konrad